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ADG714BRUZ-REEL7

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
ADG714/ADG715
–7–
ABSOLUTE MAXIMUM RATINGS
1
(T
A
= 25°C unless otherwise noted.)
V
DD
to V
SS
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
V
DD
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
V
SS
to GND . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –3.5 V
Analog Inputs
2
. . . . . . . . . . . . . . . . . V
SS
–0.3 V to V
DD
+0.3 V
or 30 mA, Whichever Occurs First
Digital Inputs
2
. . . . . . . . . . . . . . . . . . . . –0.3 V to V
DD
+0.3 V
or 30 mA, Whichever Occurs First
Peak Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
(Pulsed at 1 ms, 10% Duty Cycle Max)
Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . 30 mA
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
TSSOP Package
␪
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . 128°C/W
␪
JC
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 42°C/W
Lead Temperature, Soldering (10 sec) . . . . . . . . . . . . 300°C
Infrared Reflow (20 sec) . . . . . . . . . . . . . . . . . . . . . . . 235°C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one absolute
maximum rating may be applied at any one time.
2
Overvoltages at IN, S, or D will be clamped by internal diodes. Current should be
limited to the maximum ratings given.
PIN CONFIGURATIONS
24-Lead TSSOP
TOP VIEW
(Not to Scale)
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
SYNC
RESET
DOUT
V
SS
S8
D8
S7
D7
S6
D6
S5
D5
SCLK
V
DD
DIN
GND
S1
D1
S2
D2
S3
D3
S4
D4
ADG714
TOP VIEW
(Not to Scale)
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
A0
RESET
A1
V
SS
S8
D8
S7
D7
S6
D6
S5
D5
SCL
V
DD
SDA
GND
S1
D1
S2
D2
S3
D3
S4
D4
ADG715
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADG714/ADG715 feature proprietary ESD protection circuitry, permanent damage may occur
on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV.
D
ADG714/ADG715
–8–
ADG714 PIN FUNCTION DESCRIPTIONS
Pin No. Mnemonic Description
1 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial
clock input. These devices can accommodate serial input rates of up to 30 MHz.
2V
DD
Positive Analog Supply Voltage.
3 DIN Serial Data Input. Data is clocked into the 8-bit input register on the falling edge of the serial
clock input.
4 GND Ground Reference
5, 7, 9, 11, 14, Sx Source. May be an input or output.
16, 18, 20
6, 8, 10, 12, 13, Dx Drain. May be an input or output.
15, 17, 19
21 V
SS
Negative Analog Supply Voltage. For single supply operation this should be tied to GND.
22 DOUT Serial Data Output. This allows a number a parts to be daisy chained. Data is clocked out of
the input shift register on the rising edge of SCLK. DOUT is an open-drain output that should be
pulled to the supply with an external pull-up resistor.
23 RESET Active Low Control Input. Clears the input register and turns all switches to the OFF condition.
24 SYNC Active Low Control Input. This is the frame synchronization signal for the input data. When
SYNC goes low, it powers on the SCLK and DIN buffers and the input shift register is enabled.
Data is transferred on the falling edges of the following clocks. Taking SYNC high updates the
switches.
ADG715 PIN FUNCTION DESCRIPTIONS
Pin No. Mnemonic Description
1 SCL Serial Clock Line. This is used in conjunction with the SDA line to clock data into the 8-bit
input shift register. Clock rates of up to 400 kbit/s can be accommodated with this 2-wire
serial interface.
2V
DD
Positive Analog Supply Voltage
3 SDA Serial Data Line. This is used in conjunction with the SCL line to clock data into the 8-bit input
shift register during the write cycle and used to readback one byte of data during the read cycle. It
is a bidirectional open-drain data line which should be pulled to the supply with an external pull-
up resistor.
4 GND Ground Reference
5, 7, 9, 11, 14, Sx Source. May be an input or output.
16, 18, 20
6, 8, 10, 12, 13, Dx Drain. May be an input or output.
15, 17, 19
21 V
SS
Negative Analog Supply Voltage. For single supply operation this should be tied to GND.
22 A1 Address Input. Sets the second least significant bit of the 7-bit slave address.
23 RESET Active Low Control Input. Clears the input register and turns all switches to the OFF condition.
24 A0 Address Input. Sets the least significant bit of the 7-bit slave address.
REV.
D
ADG714/ADG715
–9–
V
DD
Most positive power supply potential.
V
SS
Most negative power supply in a dual supply
application. In single supply applications, this
should be tied to ground.
I
DD
Positive Supply Current
I
SS
Negative Supply Current
GND Ground (0 V) Reference
S Source Terminal. May be an input or output.
D Drain Terminal. May be an input or output.
R
ON
Ohmic resistance between D and S
ΔR
ON
On resistance match between any two channels,
i.e., R
ON
max–R
ON
min.
R
FLAT(ON)
Flatness is defined as the difference between the
maximum and minimum value of on resistance
as measured over the specified analog signal range.
I
S
(OFF) Source leakage current with the switch “OFF.”
I
D
(OFF) Drain leakage current with the switch “OFF.”
I
D
, I
S
(ON) Channel leakage current with the switch “ON.”
V
D
(V
S
) Analog voltage on terminals D and S
C
S
(OFF) “OFF” Switch Source Capacitance. Measured
with reference to ground.
C
D
(OFF) “OFF” Switch Drain Capacitance. Measured
with reference to ground.
C
D
, C
S
(ON) “ON” Switch Capacitance. Measured with ref-
erence to ground.
C
IN
Digital Input Capacitance
t
ON
Delay time between loading new data to the
shift register and selected switches switching on.
t
OFF
Delay time between loading new data to the
shift register and selected switches switching off.
Off Isolation A measure of unwanted signal coupling through
an “OFF” switch.
Crosstalk A measure of unwanted signal which is coupled
through from one channel to another as a result
of parasitic capacitance.
Charge A measure of the glitch impulse transferred
Injection from the digital input to the analog output
during switching.
Bandwidth The frequency at which the output is attenuated
by –3 dBs.
On Response The frequency response of the “ON” switch.
Insertion Loss The loss due to the ON resistance of the switch.
Insertion Loss = 20 log
10
(V
OUT
with switch/
V
OUT
without switch.
V
INL
Maximum input voltage for Logic 0.
V
INH
Minimum input voltage for Logic 1.
I
INL
(I
INH
) Input current of the digital input.
I
DD
Positive Supply Current
TERMINOLOGY
REV.
D
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16

ADG714BRUZ-REEL7

Mfr. #:
Buy ADG714BRUZ-REEL7
Manufacturer:
Analog Devices Inc.
Description:
Analog Switch ICs 2.5 Ohm 2.7V CMOS Octal SPST
Lifecycle:
New from this manufacturer.
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