Symbol Parameter Min Max Unit
DCLK high time for EPCQ16A, EPCQ32A, EPCQ64A,
and EPCQ128A.
3.4 or 9
(15)
— ns
t
CL
DCLK low time for EPCQ4A.
4 or 6
(14)
— ns
DCLK low time for EPCQ16A, EPCQ32A, EPCQ64A, and
EPCQ128A.
3.4 or 9
(15)
ns
t
ODIS
Output disable time after read — 7 ns
t
CLQV
Clock low to output valid for EPCQ4A. — 8 ns
Clock low to output valid for EPCQ16A, EPCQ32A,
EPCQ64A, and EPCQ128A.
— 6
t
CLQX
Output hold time for EPCQ4A. 0 — ns
Output hold time for EPCQ16A, EPCQ32A, EPCQ64A,
and EPCQ128A.
1.5 —
1.12. Programming and Configuration File Support
The Intel Quartus
®
Prime software provides programming support for EPCQ-A devices.
When you select an EPCQ-A device, the Intel Quartus Prime software automatically
generates the Programmer Object File (.pof) to program the device. The software
allows you to select the appropriate EPCQ-A device density that most efficiently stores
the configuration data for the selected FPGA.
You can program the EPCQ-A device in-system by an external microprocessor using
the SRunner software driver. The SRunner software driver is developed for embedded
EPCQ-A device programming that you can customize to fit in different embedded
systems. The SRunner software driver reads .rpd files and writes to the EPCQ-A
devices. The programming time is comparable to the Intel Quartus Prime software
programming time. Because the FPGA reads the LSB of the .rpd data first during the
configuration process, the LSB of .rpd bytes must be shifted out first during the read
bytes operation and shifted in first during the write bytes operation.
Writing and reading the .rpd file to and from the EPCQ-A device is different from the
other data and address bytes.
During the ISP of an EPCQ-A device using the Intel FPGA download cables, the cable
pulls the nCONFIG signal low to reset the FPGA and overrides the 10-kΩ pull-down
resistor on the nCE pin of the FPGA. The download cable then uses the interface pins
depending on the selected AS mode to program the EPCQ-A device. When
programming is complete, the download cable releases the interface pins of the EPCQ-
A device and the nCE pin of the FPGA and pulses the nCONFIG signal to start the
configuration process.
The FPGA can program the EPCQ-A device in-system using the JTAG interface with the
serial flash loader (SFL). This solution allows you to indirectly program the EPCQ-A
device using the same JTAG interface that is used to configure the FPGA.
(15)
3.4 ns for fast read and 9 ns for read.
1. EPCQ-A Serial Configuration Device Datasheet
CF52014 | 2018.04.11
EPCQ-A Serial Configuration Device Datasheet
33
