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AD1836AASZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25
Data Sheet AD1836A
Rev. A | Page 15 of 24
LRCLK
BCLK
DATA
SLOT 1
LEFT 0
SLOT 2
LEFT 1
SLOT 3
RIGHT 0
SLOT 4
RIGHT 1
MSB MSB–1 MSB–2
LRCLK
BCLK
DATA
32 BCLKs
128 BCLKs
Figure 5. ADC Packed Mode 128
LRCLK
BCLK
DATA
SLOT 1
LEFT 0
SLOT 2
LEFT 1
SLOT 5
RIGHT 0
SLOT 6
RIGHT 1
32 BCLKs
MSB MSB–1 MSB–2
256 BCLKs
SLOT 3 SLOT 4 SLOT 7 SLOT 8
LRCLK
BCLK
DATA
Figure 6. ADC Packed Mode 256
LRCLK
BCLK
DATA
SLOT 1
LEFT 0
SLOT 2
LEFT 1
MSB MSB–1 MSB–2
20 BCLKs
SLOT 4
RIGHT 0
SLOT 5
RIGHT 1
SLOT 3
LEFT 2
SLOT 6
RIGHT 2
LRCLK
BCLK
DATA
128 BCLKs
Figure 7. DAC Packed Mode 128
LRCLK
BCLK
DATA
SLOT 1
LEFT 0
SLOT 2
LEFT 1
MSB MSB–1 MSB–2
32 BCLKs
SLOT 4
RIGHT 0
SLOT 5
RIGHT 1
SLOT 3
LEFT 2
SLOT 6
RIGHT 2
LRCLK
BCLK
DATA
256 BCLKs
Figure 8. DAC Packed Mode 256
AD1836A Data Sheet
Rev. A | Page 16 of 24
FSTDM
ADC L0 ADC L1
AUX_ADC L0
AUX_ADC L1
ADC R0
INTERNAL
ADC R1
AUX_ADC R0
AUX_ADC R1
DAC L0 DAC L1 DAC L2
AUX_DAC L0
DAC R0 DAC R1 DAC R2
AUX_DAC R0
MSB TDM
1ST
CH
LEFT
RIGHT
I
2
S
––
MSB LEFT
BCLK
TDM
ASDATA1
TDM (OUT)
ASDATA1
DSDATA1
DSDATA1
AUX
LRCLK I
2
S
(FROM AUX ADC NO. 1)
AUX
BCLK I
2
S
(FROM AUX ADC NO. 1)
AAUXDATA1 (IN)
(FROM AUX ADC NO. 1)
AAUXDATA2 (IN)
(FROM AUX ADC NO. 2)
DAUXDATA (OUT)
(TO AUX DAC)
NOTE
AUX BCLK FREQUENCY IS 64 × FRAME RATE; TDM BCLK FREQUENCY IS 256 × FRAME RATE.
FSTDM FOLLOWS AUX LRCLK BY 3 1/2 ± 1/2 TDM BCLK IN BOTH MASTER AND SLAVE MODES.
TDM INTERFACE
AUX – I
2
S INTERFACE
MSB TDM
8TH
CH
32
32
1ST
CH
MSB TDM
8TH
CH
TDM (IN)
INTERNAL
INTERNALINTERNAL
MSB TDM
INTERNAL
INTERNAL
INTERNAL INTERNAL INTERNAL INTERNAL
I
2
S
––
MSB LEFT
I
2
S
––
MSB LEFT
I
2
S
––
MSB RIGHT
I
2
S
––
MSB RIGHT
I
2
S
––
MSB RIGHT
Figure 9. AUX Mode Timing (Note that the Clocks Are Not to Scale)
Data Sheet AD1836A
Rev. A | Page 17 of 24
30MHz
12.288MHz
SHARC IS ALWAYS
RUNNING IN SLAVE MODE
(INTERRUPT-DRIVEN)
FSYNC-TDM (RFS)
RxCLK
RxDATA
TFS (NC)
TxCLK
TxDATA
ASDATA1 ALRCLK ABCLK DSDATA1
LRCLK
BCLK
DATA
MCLK
ADC NO. 1
SLAVE
SHARC
AD1836A
MASTER
MCLK
DSDATA3/AAUXDATA2
DSDATA2/AAUXDATA1
DLRCLK/AUXLRCLK
ASDATA2/DAUXDATA
DBCLK/AUXBCLK (64f
S
)
LRCLK
BCLK
ADC NO. 2
SLAVE
LRCLK
BCLK
DATA
MCLK
DAC
DATA
MCLK
Figure 10. AUX Mode Connection to SHARC (Master Mode)
30MHz
12.288MHz
SHARC IS ALWAYS
RUNNING IN SLAVE MODE
(INTERRUPT-DRIVEN)
FSYNC-TDM (RFS)
RxCLK
RxDATA
TFS (NC)
TxCLK
TxDATA
ASDATA1 ALRCLK ABCLK DSDATA1
LRCLK
BCLK
DATA
MCLK
ADC NO. 1
MASTER
SHARC
AD1836A
SLAVE
MCLK
DSDATA3/AAUXDATA2
DSDATA2/AAUXDATA1
DLRCLK/AUXLRCLK
ASDATA2/DAUXDATA
DBCLK/AUXBCLK (64f
S
)
LRCLK
BCLK
LRCLK
BCLK
DATA
MCLK
DAC
ADC NO. 2
SLAVE
DATA
MCLK
Figure 11. AUX Mode Connection to SHARC (Slave Mode)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25

AD1836AASZ

Mfr. #:
Buy AD1836AASZ
Manufacturer:
Analog Devices Inc.
Description:
Interface - CODECs IC MultiCH96 kHz Codec
Lifecycle:
New from this manufacturer.
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