AD1836A Data Sheet
Rev. A | Page 6 of 24
Table 7. Timing Specifications
Parameter Comments Min Max Unit
MASTER CLOCK AND RESET
t
MH
MCLK High 512 × f
S
Mode 18 ns
t
ML
MCLK Low 512 × f
S
Mode 18 ns
t
MCLK
MCLK Period 512 × f
S
Mode 36 ns
f
MCLK
MCLK Frequency 512 × f
S
Mode 27 MHz
t
PDR
PD/RST
Low 5 ns
t
PDRR
PD/RST
Recovery Reset to Active Output 4500 t
MCLK
SPI PORT
t
CHH
CCLK High 10 ns
t
CHL
CCLK Low 10 ns
t
CDS
CDATA Setup To CCLK Rising 5 ns
t
CDH
CDATA Hold From CCLK Rising 5 ns
t
CLS
CLATCH
Setup To CCLK Rising 5 ns
t
CLH
CLATCH
Hold From CCLK Falling 5 ns
t
CODE
COUT Enable From CCLK Falling 10 ns
t
COD
COUT Delay From CCLK Falling 10 ns
t
COH
COUT Hold From CCLK Falling 0 ns
t
COTS
COUT Three-State From CCLK Falling 10 ns
DAC SERIAL PORT
(Normal Modes)
t
DBH
DBCLK High 15 ns
t
DBL
DBCLK Low 15 ns
f
DB
DBCLK Frequency 64 × f
S
ns
t
DLS
DLRCLK Setup To DBCLK Rising 0 ns
t
DLH
DLRCLK Hold From DBCLK Rising 10 ns
t
DDS
DSDATA Setup To DBCLK Rising 0 ns
t
DDH
DSDATA Hold From DBCLK Rising 20 ns
DAC SERIAL PORT
(Packed 128 Mode, Packed 256 Mode)
t
DBH
DBCLK High 15 ns
t
DBL
DBCLK Low 15 ns
f
DB
DBCLK Frequency 256 × f
S
ns
DLS
t
DLH
DLRCLK Hold From DBCLK Rising 10 ns
t
DDS
DSDATA Setup To DBCLK Rising 0 ns
t
DDH
DSDATA Hold From DBCLK Rising 20 ns
ADC SERIAL PORT
(Normal Modes)
t
ABD
ABCLK Delay From MCLK Transition, 256 × f
S
Mode
From MCLK Rising, 512 × f
S
Mode
15 ns
t
ALS
LRCLK Skew From ABCLK Falling –2 +2 ns
t
ABDD
ASDATA Delay From ABCLK Falling 5 ns
ADC SERIAL PORT
(Packed 128 Mode, Packed 256 Mode)
t
ABD
ABCLK Delay From MCLK Transition, 256 × f
S
Mode
From MCLK Rising, 512 × f
S
Mode
15 ns
ALS
t
ABDD
ASDATA Delay From ABCLK Falling 5 ns
ADC SERIAL PORT
(TDM Packed AUX)
t
ABD
ABCLK Delay From MCLK Transition, 256 × f
S
Mode
From MCLK Rising, 512 × f
S
Mode
15 ns
t
ALS
LRCLK Skew From ABCLK Falling –2 +2 ns
t
ABDD
ASDATA Delay From ABCLK Falling 5 ns
t
DDS
DSDATA1 Hold To ABCLK Rising 0 ns
t
DDH
DSDATA1 Hold From ABCLK Rising 7 ns
AUXILIARY INTERFACE
t
AXDS
AAUXDATA Setup To AUXBCLK Rising 7 ns
t
AXDH
AAUXDATA Hold From AUXBCLK Rising 10 ns
t
DXDD
DAUXDATA Delay From AUXBCLK Falling 25 ns
