AD1836A Data Sheet
Rev. A | Page 18 of 24
Table 11. Pin Function Changes in AUX Mode
2
2
ASDATA1(O) I
2
S Data Out, Internal ADC1 TDM Data Out, to SHARC
ASDATA2(O)/DAUXDATA(O) I
2
S Data Out, Internal ADC2 AUX—I
2
S Data Out (to External DAC)
DSDATA1(I) I
2
S Data In, Internal DAC1 TDM Data In, from SHARC
DSDATA2(I)/AAUXDATA(I) I
2
S Data In, Internal DAC2 AUX—I
2
S Data In 1 (to External ADC)
DSDATA3(I)/AAUXDATA2(I) I
2
S Data In, Internal DAC3 AUX—I
2
S Data In 2 (to External ADC)
ALRCLK(O) LRCLK for Internal ADC1, ADC2 TDM Frame Sync Out, to SHARC
ABCLK(O) BCLK for Internal ADC1, ADC2 TDM BCKL Out, to SHARC
DLRCLK(I)/AUXLRCLK(I/O) LRCLK In/Out Internal DACs AUX LRCLK In/Out, Driven by External IRCLK from ADC (in slave mode).
In master mode, driven by internal MCLK/512.
DBCLK(I)/AUXBCLK(I/O) BCLK In/Out Internal DACs AUX BCLK In/Out, Driven by External BCLK from ADC (in slave mode).
In master mode, driven by internal MCLK/8.
AUXDATA1
ASDATA2/DAUXDATA
DATA TO EXT DAC
BCLK AND LRCLK FOR
EXT DAC COMES FROM
ADC BCLK, LRCLK.
MUST BE IN I
2
S MODE.
ADC
SYNC SIGNAL DERIVED FROM AUXLRCLK USED TO
RESET INTERNAL ADC COUNTER
ASDATA1
AUXDATA
I
2
S FORMATTER
MUX
AUXLRCLK
2 AUX
CHANNELS
6-CH
DAC
6 MAIN
CHANNELS
DAC
SPORT
DSDATA1
DSDATA2
DSDATA3
LRCLK
BCLK
SPORT
SYNC
4 ADC
S
AUXBCLK
AUXLRCLK
AUXDATA2
I
2
S
DECODE
LRCLK
ABCLK
ASDATA1
ALRCLK
ABCLK
ASDATA1
DATA TO SHARC
INDICATES MUX POSITION FOR AUX-TDM MODE
MASTER/SLAVE MODE,
FROM ADC SPI PORT
FROM SHARC
FROM EXT A/D
FROM EXT A/D
DSDATA1
DSDATA2/AUXDATA1
DSDATA3/AUXDATA2
DLRCLK/AUXLRCLK
MCLK
TIMING GEN
LRCLK BCLK
DBCLK/AUXBCLK
MUX
AUXBCLK
MUX
I
2
S
Figure 12. Extended TDM Mode (Internal Flow Diagram)