HEF4794B_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 7 August 2012 3 of 17
NXP Semiconductors
HEF4794B-Q100
8-stage shift-and-store register LED driver
5. Pinning information
5.1 Pinning
5.2 Pin description
Fig 4. Pin configuration
+()%4
675 9
''
2(
&
43
43 43
43 43
43 43
43 46
9
6
46
DDD
Table 2. Pin description
Symbol Pin Description
D 2 serial input
QP0 to QP7 4, 5, 6, 7, 14, 13, 12, 11 parallel output
QS1 9 serial output
QS2 10 serial output
CP 3 clock input
STR 1 strobe input
OE 15 output enable input
V
DD
16 supply voltage
V
SS
8 ground (0 V)
HEF4794B_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 7 August 2012 4 of 17
NXP Semiconductors
HEF4794B-Q100
8-stage shift-and-store register LED driver
6. Functional description
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state;
= LOW-to-HIGH clock transition; = HIGH-to-LOW clock transition.
[2] Q6S = the data in register stage 6 before the LOW to HIGH clock transition.
[3] Q7S = the data in register stage 7 before the HIGH to LOW clock transition.
Table 3. Function table
[1]
Input Parallel output Serial output
CP OE STR D QP0 QPn QS1
[2]
QS2
[3]
L X X Z Z Q6S no change
LXXZZn.c.Q7S
H L X no change no change Q6S no change
HHLZQPn 1 Q6S no change
HHHL QPn 1 Q6S no change
H H H no change no change no change Q7S
Fig 5. Timing diagram
001aag801
clock input
data input
strobe input
output enable
input
internal Q0S
(FF0)
QP0 output
internal Q6S
(FF6)
QP6 output
serial QS1
output
serial QS2
output
Z-state
Z-state
HEF4794B_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 7 August 2012 5 of 17
NXP Semiconductors
HEF4794B-Q100
8-stage shift-and-store register LED driver
7. Limiting values
[1] For SO16 package: P
tot
derates linearly with 8 mW/K above 70 C.
8. Recommended operating conditions
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
V
DD
supply voltage 0.5 +18 V
I
IK
input clamping current V
I
< 0.5 V or V
I
>V
DD
+ 0.5 V - 10 mA
V
I
input voltage 0.5 V
DD
+ 0.5 V
I
OK
output clamping current QSn outputs;
V
O
< 0.5 V or V
O
>V
DD
+ 0.5 V
- 10 mA
QPn outputs; V
O
< 0.5 V - 40 mA
I
I
input leakage current - 10 mA
I
O
output current QSn outputs - 10 mA
QPn outputs - 40 mA
T
stg
storage temperature 65 +150 C
T
amb
ambient temperature 40 +125 C
P
tot
total power dissipation T
amb
= 40 C to +125 C
[1]
-500mW
P power dissipation per output - 100 mW
Table 5. Recommended operating conditions
Symbol Parameter Conditions Min Max Unit
V
DD
supply voltage 3 15 V
V
I
input voltage 0 V
DD
V
T
amb
ambient temperature in free air 40 +125 C
t/V input transition rise and fall rate V
DD
= 5 V - 3.75 s/V
V
DD
= 10 V - 0.5 s/V
V
DD
= 15 V - 0.08 s/V

HEF4794BT-Q100J

Mfr. #:
Manufacturer:
Nexperia
Description:
Counter Shift Registers HEF4794BT-Q100/SO16/REEL 13" Q
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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