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HEF4794BT-Q100J

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18
HEF4794B_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 7 August 2012 6 of 17
NXP Semiconductors
HEF4794B-Q100
8-stage shift-and-store register LED driver
9. Static characteristics
Table 6. Static characteristics
V
SS
= 0 V; V
I
= V
SS
or V
DD
; unless otherwise specified.
Symbol Parameter Conditions V
DD
T
amb
= 40 C T
amb
= 25 C T
amb
= 85 C T
amb
= 125 C Unit
Min Max Min Max Min Max Min Max
V
IH
HIGH-level
input voltage
I
O
< 1 A 5 V 3.5 - 3.5 - 3.5 - 3.5 - V
10 V 7.0 - 7.0 - 7.0 - 7.0 - V
15 V 11.0 - 11.0 - 11.0 - 11.0 - V
V
IL
LOW-level
input voltage
I
O
< 1 A 5 V - 1.5 - 1.5 - 1.5 - 1.5 V
10 V - 3.0 - 3.0 - 3.0 - 3.0 V
15 V - 4.0 - 4.0 - 4.0 - 4.0 V
V
OH
HIGH-level
output voltage
QSn outputs;
I
O
< 1 A
5 V 4.95 - 4.95 - 4.95 - 4.95 - V
10 V 9.95 - 9.95 - 9.95 - 9.95 - V
15 V 14.95 - 14.95 - 14.95 - 14.95 - V
V
OL
LOW-level
output voltage
QSn outputs;
I
O
< 1 A
5 V - 0.05 - 0.05 - 0.05 - 0.05 V
10 V - 0.05 - 0.05 - 0.05 - 0.05 V
15 V - 0.05 - 0.05 - 0.05 - 0.05 V
QPn outputs;
I
O
< 20 mA
5 V - 0.75 - 0.75 - 1.5 - 1.5 V
10 V - 0.75 - 0.75 - 1.5 - 1.5 V
15 V - 0.75 - 0.75 - 1.5 - 1.5 V
I
OH
HIGH-level
output current
QSn outputs
V
O
= 2.5 V 5 V - 1.7 - 1.4 - 1.1 - 1.1 mA
V
O
= 4.6 V 5 V - 0.64 - 0.5 - 0.36 - 0.36 mA
V
O
= 9.5 V 10 V - 1.6 - 1.3 - 0.9 - 0.9 mA
V
O
= 13.5 V 15 V - 4.2 - 3.4 - 2.4 - 2.4 mA
I
OL
LOW-level
output current
QSn outputs
V
O
= 0.4 V 5 V 0.64 - 0.5 - 0.36 - 0.36 - mA
V
O
= 0.5 V 10 V 1.6 - 1.3 - 0.9 - 0.9 - mA
V
O
= 1.5 V 15 V 4.2 - 3.4 - 2.4 - 2.4 - mA
I
I
input leakage
current
15 V - 0.1 - 0.1 - 1.0 - 1.0 A
I
OZ
OFF-state
output current
QPn output
is HIGH;
V
O
=15V
5 V - 2 - 2 - 15 - 15 A
10 V - 2 - 2 - 15 - 15 A
15 V - 2 - 2 - 15 - 15 A
I
DD
supply current I
O
= 0 A 5 V - 5 - 5 - 150 - 150 A
10 V - 10 - 10 - 300 - 300 A
15 V - 20 - 20 - 600 - 600 A
C
I
input
capacitance
-----7.5---pF
HEF4794B_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 7 August 2012 7 of 17
NXP Semiconductors
HEF4794B-Q100
8-stage shift-and-store register LED driver
10. Dynamic characteristics
Table 7. Dynamic characteristics
V
SS
= 0 V; T
amb
= 25
C unless otherwise specified. For test circuit, see Figure 10.
Symbol Parameter Conditions V
DD
Extrapolation formula Min Typ Max Unit
t
PHL
HIGH to LOW
propagation delay
CP to QS1;
see Figure 6
5 V
[1]
132 ns + (0.55 ns/pF)C
L
-160320ns
10 V 53 ns + (0.23 ns/pF)C
L
- 65 130 ns
15 V 37 ns + (0.16 ns/pF)C
L
- 4590ns
CP to QS2;
see Figure 6
5 V 92 ns + (0.55 ns/pF)C
L
-120240ns
10 V 39 ns + (0.23 ns/pF)C
L
- 50 100 ns
15 V 32 ns + (0.16 ns/pF)C
L
- 4080ns
t
PLH
LOW to HIGH
propagation delay
CP to QS1;
see Figure 6
5 V
[1]
102 ns + (0.55 ns/pF)C
L
-130260ns
10 V 44 ns + (0.23 ns/pF)C
L
-55110ns
15 V 32 ns + (0.16 ns/pF)C
L
- 4080ns
CP to QS2;
see Figure 6
5 V 102 ns + (0.55 ns/pF)C
L
-130260ns
10 V 49 ns + (0.23 ns/pF)C
L
- 60 120 ns
15 V 37 ns + (0.16 ns/pF)C
L
- 4590ns
t
PZL
OFF-state to LOW
propagation delay
CP to QPn;
see Figure 6
5 V - 240 480 ns
10 V - 80 160 ns
15 V - 55 110 ns
STR to QPn;
see Figure 7
5 V - 140 280 ns
10 V - 70 140 ns
15 V - 55 110 ns
t
PLZ
LOW to OFF-state
propagation delay
CP to QPn;
see Figure 6
5 V - 170 340 ns
10 V - 75 150 ns
15 V - 60 120 ns
STR to QPn;
see Figure 7
5 V - 100 200 ns
10 V - 40 100 ns
15 V - 35 70 ns
t
en
enable time OE to QPn;
see Figure 8
5 V
[2]
-100200ns
10 V - 55 110 ns
15 V - 50 100 ns
t
dis
disable time OE to QPn;
see Figure 8
5 V
[2]
- 80 160 ns
10 V - 40 80 ns
15 V - 30 60 ns
t
t
transition time QS1, QS2;
see Figure 6
5 V
[1]
[3]
35 ns + (1.00 ns/pF)C
L
- 85 170 ns
10 V 19 ns + (0.42 ns/pF)C
L
- 4080ns
15 V 16 ns + (0.28 ns/pF)C
L
- 3060ns
HEF4794B_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 7 August 2012 8 of 17
NXP Semiconductors
HEF4794B-Q100
8-stage shift-and-store register LED driver
[1] The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (C
L
in pF).
[2] t
en
is the same as t
PZL
and t
dis
is the same as t
PLZ
[3] t
t
is the same as t
TLH
and t
THL
t
W
pulse width CP; LOW and
HIGH;
see Figure 6
5 V 60 30 - ns
10 V 30 15 - ns
15 V 24 12 - ns
STR; HIGH;
see Figure 7
5 V 80 40 - ns
10 V 60 30 - ns
15 V 24 12 - ns
t
su
set-up time D to CP;
see Figure 9
5 V 60 30 - ns
10 V 20 10 - ns
15 V 15 5 - ns
t
h
hold time D to CP;
see Figure 9
5 V +5 15 - ns
10 V 20 5 - ns
15 V 20 5 - ns
f
clk(max)
maximum clock
frequency
CP; see Figure 6 5 V 5 10 - MHz
10 V 11 22 - MHz
15 V 14 28 - MHz
Table 7. Dynamic characteristics
…continued
V
SS
= 0 V; T
amb
= 25
C unless otherwise specified. For test circuit, see Figure 10.
Symbol Parameter Conditions V
DD
Extrapolation formula Min Typ Max Unit
Table 8. Dynamic power dissipation
P
D
can be calculated from the formulas shown. V
SS
= 0 V; t
r
= t
f
20 ns; T
amb
= 25
C.
Symbol Parameter V
DD
Typical formula Where
P
D
dynamic power dissipation 5 V P
D
= 1200 f
i
+ (f
o
C
L
) V
DD
2
Wf
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
(f
o
C
L
) = sum of the outputs;
V
DD
= supply voltage in V.
10 V P
D
= 5550 f
i
+ (f
o
C
L
) V
DD
2
W
15 V P
D
= 15000 f
i
+ (f
o
C
L
) V
DD
2
W
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18

HEF4794BT-Q100J

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Buy HEF4794BT-Q100J
Manufacturer:
Nexperia
Description:
Counter Shift Registers HEF4794BT-Q100/SO16/REEL 13" Q
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New from this manufacturer.
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