EProClock
®
PCI Express Gen 2 & Gen 3 Generator
SL28PCIe26
DOC#: SP-AP-0774 (Rev. 0.2) Page 1 of 14
400 West Cesar Chavez, Austin, TX 78701 1+(512) 416-8500 1+(512) 416-9669 www.silabs.com
Features
Optimized 100 MHz Operating Frequencies to Meet the
Next Generation PCI-Express Gen 2 & Gen 3
Low power push-pull type differential output buffers
Integrated voltage regulator
Integrated resistors on differential clocks
Four 100-MHz differential PCI-Express clocks
Low jitter (<50pS)
EProClock
®
Programmable Technology
•I
2
C support with readback capabilities
Triangular Spread Spectrum profile for maximum
electromagnetic interference (EMI) reduction
25MHz Crystal Input or Clock input
Industrial Temperature -40
o
C to 85
o
C
3.3V Power supply
32-pin QFN package
Block Diagram
Pin Configuration
SL28PCIe26
DOC#: SP-AP-0774 (Rev. 0.2) Page 2 of 14
32-QFN Pin Definitions
EProClock
®
Programmable Technology
EProClock
®
is the world’s first non-volatile programmable
clock. The EProClock
®
technology allows board designer to
promptly achieve optimum compliance and clock signal
integrity; historically, attainable typically through device and/or
board redesigns.
EProClock
®
technology can be configured through SMBus or
hard coded.
Features:
- > 4000 bits of configurations
- Can be configured through SMBus or hard coded
- Custom frequency sets
- Differential skew control on true or compliment or both
- Differential duty cycle control on true or compliment or both
- Differential amplitude control
- Differential slew rate control
- Program different spread profiles and modulation rates
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers are individually enabled or disabled. The
registers associated with the Serial Data Interface initialize to
Pin No.
Name Type Description
1 VDD PWR 3.3V Power Supply
2 VSS GND Ground
3 NC NC No Connect.
4 NC NC No Connect.
5 VDD PWR 3.3V Power Supply
6 NC NC No Connect.
7 NC NC No Connect.
8 VSS GND Ground
9 VSS GND Ground
10 SRC0 O, DIF 100MHz True differential serial reference clock
11 SRC0# O, DIF 100MHz Complement differential serial reference clock
12 VSS GND Ground
13 SRC1 O, DIF 100MHz True differential serial reference clock
14 SRC1# O, DIF 100MHz Complement differential serial reference clock
15 VDD PWR 3.3V Power Supply
16 NC NC No Connect.
17 VDD PWR 3.3V Power Supply
18 VDD PWR 3.3V Power Supply
19 SRC2# O, DIF 100MHz Complement differential serial reference clock
20 SRC2 O, DIF 100MHz True differential serial reference clock
21 VSS GND Ground
22 SRC3# O, DIF 100MHz Complement differential serial reference clock
23 SRC3 O, DIF 100MHz True differential serial reference clock
24 VDD PWR 3.3V Power Supply
25 CKPWRGD/PD# I 3.3V LVTTT input pin. When PD# is asserted low, the device will power down.
26 VSS GND Ground
27 XOUT O, SE 25MHz Crystal output, Float XOUT if using CLKIN (Clock Input)
28 XIN/CLKIN I 25MHz Crystal input or 3.3V, 25MHz Clock Input
29 VDD PWR 3.3V Power Supply
30 NC NC No Connect.
31 SDATA I/O SMBus compatible SDATA
32 SCLK I SMBus compatible SCLOCK
SL28PCIe26
DOC#: SP-AP-0774 (Rev. 0.2) Page 3 of 14
their default setting at power-up. The use of this interface is
optional. Clock device register changes are normally made at
system initialization, if any are required. The interface cannot
be used during system operation for power management
functions.
Data Protocol
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, access the bytes in sequential
order from lowest to highest (most significant bit first) with the
ability to stop after any complete byte is transferred. For byte
write and byte read operations, the system controller can
access individually indexed bytes. The offset of the indexed
byte is encoded in the command code described in Table 1.
The block write and block read protocol is outlined in Table 2
while Table 3 outlines byte write and byte read protocol. The
slave receiver address is 11010010 (D2h).
Table 1. Command Code Definition
Bit Description
7 0 = Block read or block write operation, 1 = Byte read or byte write operation
(6:0) Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '0000000'
Table 2. Block Read and Block Write Protocol
Block Write Protocol Block Read Protocol
Bit Description Bit Description
1Start 1Start
8:2 Slave address–7 bits 8:2 Slave address–7 bits
9 Write 9 Write
10 Acknowledge from slave 10 Acknowledge from slave
18:11 Command Code–8 bits 18:11 Command Code–8 bits
19 Acknowledge from slave 19 Acknowledge from slave
27:20 Byte Count–8 bits 20 Repeat start
28 Acknowledge from slave 27:21 Slave address–7 bits
36:29 Data byte 1–8 bits 28 Read = 1
37 Acknowledge from slave 29 Acknowledge from slave
45:38 Data byte 2–8 bits 37:30 Byte Count from slave–8 bits
46 Acknowledge from slave 38 Acknowledge
.... Data Byte /Slave Acknowledges 46:39 Data byte 1 from slave–8 bits
.... Data Byte N–8 bits 47 Acknowledge
.... Acknowledge from slave 55:48 Data byte 2 from slave–8 bits
.... Stop 56 Acknowledge
.... Data bytes from slave / Acknowledge
.... Data Byte N from slave–8 bits
.... NOT Acknowledge
.... Stop
Table 3. Byte Read and Byte Write Protocol
Byte Write Protocol Byte Read Protocol
Bit Description Bit Description
1Start 1Start
8:2 Slave address–7 bits 8:2 Slave address–7 bits
9Write 9Write
10 Acknowledge from slave 10 Acknowledge from slave
18:11 Command Code–8 bits 18:11 Command Code–8 bits
19 Acknowledge from slave 19 Acknowledge from slave
27:20 Data byte–8 bits 20 Repeated start

SL28PCIe26ALCT

Mfr. #:
Manufacturer:
Silicon Labs
Description:
Clock Generators & Support Products PCIe clock g., Xin(25M) -->4 PCIe out (gen.3)
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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