DOC#: SP-AP-0774 (Rev. 0.2) Page 10 of 14
AC Electrical Specifications
Parameter Description Condition Min. Max. Unit
Crystal
L
ACC
Long-term Accuracy Measured at VDD/2 differential – 250 ppm
Clock Input
T
DC
CLKIN Duty Cycle Measured at VDD/2 47 53 %
T
R
/T
F
CLKIN Rise and Fall Times Measured between 0.2V
DD
and 0.8V
DD
0.5 4.0 V/ns
T
CCJ
CLKIN Cycle to Cycle Jitter Measured at VDD/2 – 250 ps
T
LTJ
CLKIN Long Term Jitter Measured at VDD/2 – 350 ps
V
IH
Input High Voltage XIN / CLKIN pin 2 VDD+0.3 V
V
IL
Input Low Voltage XIN / CLKIN pin – 0.8 V
I
IH
Input HighCurrent XIN / CLKIN pin, VIN = VDD – 35 uA
I
IL
Input LowCurrent XIN / CLKIN pin, 0 < VIN <0.8 -35 – uA
SRC at 0.7V
T
DC
Duty Cycle Measured at 0V differential 45 55 %
T
PERIOD
Period Measured at 0V differential at 0.1s
9.99900 10.0010
ns
T
PERIODSS
Period, SSC Measured at 0V differential at 0.1s
10.02406 10.02607
ns
T
PERIODAbs
Absolute Period Measured at 0V differential at 1 clock
9.87400 10.1260
ns
T
PERIODSSAbs
Absolute Period, SSC Measured at 0V differential at 1 clock
9.87406 10.1762
ns
T
CCJ
Cycle to Cycle Jitter Measured at 0V differential – 125 ps
RMS
GEN1
Output PCIe* Gen1 REFCLK phase
jitter
BER = 1E-12 (including PLL BW 8 - 16
MHz, ζ = 0.54, Td=10 ns,
Ftrk=1.5 MHz)
0108ps
RMS
GEN2
Output PCIe* Gen2 REFCLK phase
jitter
Includes PLL BW 8 - 16 MHz, Jitter
Peaking = 3dB, ζ = 0.54, Td=10 ns),
Low Band, F < 1.5MHz
03.0ps
RMS
GEN2
Output PCIe* Gen2 REFCLK phase
jitter
Includes PLL BW 8 - 16 MHz, Jitter
Peaking = 3dB, ζ = 0.54, Td=10 ns),
Low Band, F < 1.5MHz
03.1ps
RMS
GEN3
Output phase jitter impact – PCIe*
Gen3
Includes PLL BW 2 - 4 MHz,
CDR = 10MHz)
01.0ps
L
ACC
Long Term Accuracy Measured at 0V differential – 100 ppm
T
R
/ T
F
Rising/Falling Slew Rate Measured differentially from ±150 mV 2.5 8 V/ns
V
HIGH
Voltage High 1.15 V
V
LOW
Voltage Low –0.3 – V
V
OX
Crossing Point Voltage at 0.7V Swing 300 550 mV
ENABLE/DISABLE and SET-UP
T
STABLE
Clock Stabilization from Power-up – 1.8 ms
T
SS
Stopclock Set-up Time 10.0 – ns
