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74HC4017N,652

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24
74HC_HCT4017 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 4 — 10 December 2013 4 of 24
NXP Semiconductors 74HC4017; 74HCT4017
Johnson decade counter with 10 decoded outputs
Fig 5. Timing diagram
001aah244
CP0 INPUT
CP1 INPUT
MR INPUT
Q0 OUTPUT
Q1 OUTPUT
Q2 OUTPUT
Q3 OUTPUT
Q4 OUTPUT
Q5 OUTPUT
Q6 OUTPUT
Q7 OUTPUT
Q8 OUTPUT
Q9 OUTPUT
Q5-9 OUTPUT
74HC_HCT4017 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 4 — 10 December 2013 5 of 24
NXP Semiconductors 74HC4017; 74HCT4017
Johnson decade counter with 10 decoded outputs
5. Pinning information
5.1 Pinning
5.2 Pin description
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 6. Pin configuration DIP16, SO16 and (T)SSOP16 Fig 7. Pin configuration DHVQFN16
74HC4017
74HCT4017
Q5 V
CC
Q1 MR
Q0 CP0
Q2 CP1
Q6 Q5-9
Q7 Q9
Q3 Q4
GND Q8
001aah238
1
2
3
4
5
6
7
8
10
9
12
11
14
13
16
15
001aah241
74HC4017
74HCT4017
Q3 Q4
Q7 Q9
Q6 Q5-9
Q2 CP1
Q0 CP0
Q1 MR
GND
Q8
Q5
V
CC
Transparent top view
7 10
6 11
5 12
4
13
3 14
2 15
8
9
1
16
terminal 1
index area
GND
(1)
Table 2. Pin description
Symbol Pin Description
Q[0:9] 3, 2, 4, 7, 10, 1, 5, 6, 9, 11 decoded output
GND 8 ground (0 V)
Q
5-9 12 carry output (active LOW)
CP
1 13 clock input (HIGH-to-LOW edge-triggered)
CP0 14 clock input (LOW-to-HIGH edge-triggered)
MR 15 master reset input (active HIGH)
V
CC
16 supply voltage
74HC_HCT4017 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 4 — 10 December 2013 6 of 24
NXP Semiconductors 74HC4017; 74HCT4017
Johnson decade counter with 10 decoded outputs
6. Functional description
[1] H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
= LOW-to-HIGH transition;
= HIGH-to-LOW transition;
7. Limiting values
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] P
tot
derates linearly with 12 mW/K above 70 C.
[3] P
tot
derates linearly with 8 mW/K above 70 C.
[4] P
tot
derates linearly with 5.5 mW/K above 60 C.
[5] P
tot
derates linearly with 4.5 mW/K above 60 C.
Table 3. Function table
[1]
MR CP0 CP1 Operation
HXXQ0 = Q
5-9 = HIGH;
Q1 to Q9 = LOW
LH counter advances
L L counter advances
L L X no change
L X H no change
LH no change
L L no change
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
V
CC
supply voltage 0.5 +7 V
I
IK
input clamping current V
I
< 0.5 V or V
I
>V
CC
+0.5 V
[1]
- 20 mA
I
OK
output clamping current V
O
< 0.5 V or V
O
>V
CC
+0.5V
[1]
- 20 mA
I
O
output current 0.5 V < V
O
< V
CC
+0.5V - 25 mA
I
CC
supply current - 50 mA
I
GND
ground current 50 - mA
T
stg
storage temperature 65 +150 C
P
tot
total power dissipation T
amb
= 40 C to +125 C
DIP16 package
[2]
- 750 mW
SO16 package
[3]
- 500 mW
(T)SSOP16 package
[4]
- 500 mW
DHVQFN16 package
[5]
- 500 mW
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24

74HC4017N,652

Mfr. #:
Buy 74HC4017N,652
Manufacturer:
NXP Semiconductors
Description:
Counter ICs 5ST JOHNSON COUNTER 10 DECODED OUTPUTS
Lifecycle:
New from this manufacturer.
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