NCV7704, NCV7714
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Table 8. COMMAND BYTE, REGISTER ADDRESS
A[5:0] Access Description Content
00h R/W
Control Register
CONTROL_0
Device mode control, Bridge outputs control
01h R/W
Control Register
CONTROL_1
High−side outputs control, ECM control (NCV7714 only)
02h R/W
Control Register
CONTROL_2
Bridge outputs recovery control, PWM enable, ECM setup (NCV7714 only)
03h R/W
Control Register
CONTROL_3
High−side outputs recovery control, PWM enable, Current Sense selection
08h R/W
PWM Control Register
PWM_4
PWM control register for OUT4
09h R/W
PWM Control Register
PWM_5/6
PWM control register for OUT5/6
10h R/RC
Status Register
STATUS_0
Bridge outputs Overcurrent diagnosis
11h R/RC
Status Register
STATUS_1
Bridge outputs Underload diagnosis
12h R/RC
Status Register
STATUS_2
HS outputs Overcurrent and Underload diagnosis, Vs Over− and Under-
voltage, EC−mirror (NCV7714 only)
3Fh R/W
Configuration Register
CONFIG
Mask bits for global fault bits
Table 9. CHIP ID INFORMATION
A[5:0] Access Description Content
00h RDID ID header 4300h
01h RDID Version 0000h
02h RDID Product Code 1 7700h
03h RDID Product Code 2 0400h (NCV7704)
0E00h (NCV7714)
3Eh RDID SPI−Frame ID 0200h
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Table 10. GLOBAL STATUS BYTE CONTENT
FLT Global Fault Bit
0 No fault Condition
Failures of the Global Status Byte, bits [6:0] are always linked to the Global Fault Bit FLT. This bit
is generated by an OR combination of all failure bits of the device (RESB inverted). It is reflected
via the SO pin while CSB is held low and NO clock signal is present (before first positive edge of
SCLK). The flag will remain valid as long as CSB is held low. This operation does not cause the
Transmission error Flag in the Global Status Byte to be set. Signals TW and ULD can be masked
.
1 Fault Condition
TF SPI Transmission Error
0 No Error
If the number of clock pulses within the previous frame was unequal 0 (FLT polling) or 24. The
frame was ignored and this flag was set.
1 Error
RESB Reset Bar (Active low)
0 Reset
Bit is set to “0” after a Power−on−Reset or a stuck−at−1 fault at SI (SPI−input data = FFFFFFh)
has been detected. All outputs are disabled.
1 Normal Operation
TSD Overtemperature Shutdown
0 No Thermal Shutdown
Thermal Shutdown Status indication. In case of a Thermal Shutdown, all output drivers including
the charge pump output are deactivated (high impedance). The TSD bit has to be cleared thru a
SW reset to reactivate the output drivers and the chargepump output.
1 Thermal Shutdown
TW Thermal Warning
0 No Thermal Warning
This bit indicates a pre−warning level of the junction temperature. It is maskable by the
Configuration Register (CONFIG.NO_TW).
1 Thermal Warning
UOV_OC VS Monitoring, Overcurrent Status
0 No Fault
This bit represents a logical OR combination of under−/overvoltage signals (VS) and overcurrent
signals.
1 Fault
ULD Underload
0 No Underload
This bit represents a logical OR combination of all underload signals. It is maskable by the
Configuration Register (CONFIG.NO_ULDx). It is also possible to deactivate this flag for HS1 or
LS1, only (CONFIG.NO_ULD_HS1/LS1).
1 Underload
NRDY Not Ready
0 Device Ready
After transition from Standby to Active mode, an internal timer is started to allow the internal
chargepump to settle before any outputs can be activated. This bit is cleared automatically after
the startup is completed.
1 Device Not Ready
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SPI REGISTERS CONTENT
CONTROL_0 Register
Address: 00h
Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Access type RW RW RW RW RW RW RW
Bit name HS1 LS1 HS2 LS2 HS3 LS3 0 0 0 0 0 0 0 0 0 MODE
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HS/LS Outputs
OUT1−3 Driver
Control
HSx LSx Description Remark
0 0 default OUTx High impedance
If a driver is enabled by the control register AND the
corresponding PWM enable bit is set in CONTROL_2
register, the output is only activated if PWM1 (PWM2)
input signal is high. Since OUT1..OUT3 are
half−bridge outputs, activating both HS and LS at the
same time is prevented by internal logic.
0 1 LSx enabled
1 0 HSx enabled
1 1 OUTx High impedance
Mode Control
MODE Description Remark
0 default Standby
If MODE is set, the device is switched to Active mode.
Resetting MODE forces the device to transition into
Standby mode, all internal memory is cleared and all
output stages are switched into their default state (off).
1 Active

NCV7704DQR2G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Display Drivers & Controllers MIRROR DRIVER LOW CONTENT
Lifecycle:
New from this manufacturer.
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