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CY7C199D-10VXI

P1-P3P4-P6P7-P9P10-P12P13-P15
CY7C199D
256-Kbit (32 K × 8) Static RAM
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 38-05471 Rev. *L Revised November 28, 2014
256-Kbit (32 K × 8) Static RAM
Features
■ Temperature range
❐ –40 °C to 85 °C
■ Pin and function compatible with CY7C199C
■ High speed
❐ t
AA
= 10 ns
■ Low active power
❐ I
CC
= 80 mA at 10 ns
■ Low CMOS standby power
❐ I
SB2
= 3 mA
■ 2.0 V data retention
■ Automatic power-down when deselected
■ Complementary metal oxide semiconductor (CMOS) for
optimum speed/power
■ Transistor-transistor logic (TTL) compatible inputs and outputs
■ Easy memory expansion with CE and OE features
■ Available in Pb-free 28-pin 300-Mil-wide molded small outline
J-lead package (SOJ) and 28-pin thin small outline package
(TSOP) I packages
Functional Description
The CY7C199D is a high performance CMOS static RAM
organized as 32,768 words by 8-bits. Easy memory expansion is
provided by an active LOW chip enable (CE), an active LOW
output enable (OE
) and tri-state drivers. This device has an
automatic power-down feature, reducing the power consumption
when deselected. The input and output pins (I/O
0
through I/O
7
)
are placed in a high impedance state when the device is
deselected (CE
HIGH), the outputs are disabled (OE HIGH), or
during a write operation (CE
LOW and WE LOW).
Write to the device by taking chip enable (CE) and write enable
(WE
) inputs LOW. Data on the eight I/O pins (I/O
0
through I/O
7
)
is then written into the location specified on the address pins (A
0
through A
14
).
Read from the device by taking chip enable (CE
) and output
enable (OE
) LOW while forcing write enable (WE) HIGH. Under
these conditions, the contents of the memory location specified
by the address pins appears on the I/O pins.
The CY7C199D device is suitable for interfacing with processors
that have TTL I/P levels. It is not suitable for processors that
require CMOS I/P levels. Please see Electrical Characteristics
on page 4 for more details and suggested alternatives.
For a complete list of related documentation, click here.
Logic Block Diagram
I/O
0
I/O
1
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
CY7C199D
Document Number: 38-05471 Rev. *L Page 2 of 15
Contents
Pin Configurations ...........................................................3
Selection Guide ................................................................3
Maximum Ratings .............................................................4
Operating Range ............................................................... 4
Electrical Characteristics .................................................4
Capacitance ......................................................................5
Thermal Resistance ..........................................................5
AC Test Loads and Waveforms .......................................5
Data Retention Characteristics ....................................... 6
Data Retention Waveform ................................................6
Switching Characteristics ................................................7
Switching Waveforms ...................................................... 8
Truth Table ......................................................................10
Ordering Information ...................................................... 10
Ordering Code Definitions ......................................... 10
Package Diagrams .......................................................... 11
Acronyms ........................................................................ 13
Document Conventions ................................................. 13
Units of Measure ....................................................... 13
Document History Page ................................................. 14
Sales, Solutions, and Legal Information ...................... 15
Worldwide Sales and Design Support ....................... 15
Products .................................................................... 15
PSoC® Solutions ...................................................... 15
Cypress Developer Community ................................. 15
Technical Support ..................................................... 15
CY7C199D
Document Number: 38-05471 Rev. *L Page 3 of 15
Pin Configurations
Figure 1. 28-pin SOJ pinout (Top View) Figure 2. 28-pin TSOP I pinout (Top View)
Selection Guide
Description -10 (Industrial) Unit
Maximum access time 10 ns
Maximum operating current 80 mA
Maximum CMOS standby current 3mA
22
23
24
25
26
27
28
1
2
4
7
8
9
13
12
11
10
14
17
16
15
5
6
18
21
20
19
A
0
CE
I/O
7
OE
A
1
A
2
A
3
A
4
I/O
6
I/O
5
I/O
4
WE
V
CC
A
5
A
6
A
7
A
10
A
11
A
12
A
13
I/O
1
I/O
2
GND
I/O
3
A
8
A
14
I/O
0
A
9
3
TSOP I
Top View
(not to scale)
1
2
3
4
5
6
7
8
9
11
14
15
16
20
19
18
17
21
24
23
22
12
13
25
28
27
26
V
CC
WE
A
4
A
5
A
6
A
7
A
8
A
9
A
3
A
2
A
1
A
10
A
11
A
12
A
13
A
14
I/O
2
GND
I/O
3
I/O
4
I/O
7
CE
A
0
OE
I/O
0
I/O
5
I/O
6
I/O
1
10
P1-P3P4-P6P7-P9P10-P12P13-P15

CY7C199D-10VXI

Mfr. #:
Buy CY7C199D-10VXI
Manufacturer:
Cypress Semiconductor
Description:
SRAM 256Kb 10ns 32K x 8 SRAM
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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