Document Number: 38-05471 Rev. *L Page 7 of 15
Switching Characteristics
Over the operating range
Parameter
[7]
Description
CY7C199D-10
Unit
Min Max
Read Cycle
t
power
[8]
V
CC(typical)
to the first access 100 – s
t
RC
Read cycle time 10 – ns
t
AA
Address to data valid – 10 ns
t
OHA
Data hold from address change 3 – ns
t
ACE
CE LOW to data valid – 10 ns
t
DOE
OE LOW to data valid – 5 ns
t
LZOE
[9]
OE LOW to low Z 0 – ns
t
HZOE
[9, 10]
OE HIGH to high Z – 5 ns
t
LZCE
[9]
CE LOW to low Z 3 – ns
t
HZCE
[9, 10]
CE HIGH to high Z – 5 ns
t
PU
[11]
CE LOW to power-up 0 – ns
t
PD
[11]
CE HIGH to power-down – 10 ns
Write Cycle
[12, 13]
t
WC
Write cycle time 10 – ns
t
SCE
CE LOW to write end 7 – ns
t
AW
Address setup to write end 7 – ns
t
HA
Address hold from write end 0 – ns
t
SA
Address setup to write start 0 – ns
t
PWE
WE pulse width 7 – ns
t
SD
Data setup to write end 6 – ns
t
HD
Data hold from write end 0 – ns
t
HZWE
[9]
WE LOW to high Z – 5 ns
t
LZWE
[9, 10]
WE HIGH to low Z 3 – ns
Notes
7. Test conditions assume signal transition time of 3 ns or less for all speeds, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the
specified I
OL
/I
OH
and 30-pF load capacitance.
8. t
POWER
gives the minimum amount of time that the power supply should be at typical V
CC
values until the first memory access can be performed.
9. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
10. t
HZOE
, t
HZCE
, and t
HZWE
are specified with C
L
= 5 pF as in part (b) of Figure 3 on page 5. Transition is measured 200 mV from steady-state voltage.
11. This parameter is guaranteed by design and is not tested.
12. The internal write time of the memory is defined by the overlap of CE
LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write
by going HIGH. The data input setup and hold timing should be referenced to the rising edge of the signal that terminates the write.
13. The minimum write cycle time for Write Cycle No. 3 (WE
controlled, OE LOW) is the sum of t
HZWE
and t
SD
.
