1. General description
The 74LVCH162374A is a 16-bit edge triggered flip-flop featuring separate D-type inputs
for each flip-flop and 3-state outputs for bus-oriented applications. The device consists of
two sections of 8 edge-triggered flip-flops. A clock (CP) input and an output enable (OE
)
are provided for each octal. Inputs can be driven from either 3.3 V or 5 V devices. When
disabled, up to 5.5 V can be applied to the outputs. These features allow the use of these
devices in mixed 3.3 V and 5 V applications. The flip-flops store the state of their
individual D-inputs that meet the set-up and hold time requirements on the LOW to HIGH
CP transition. When OE
is LOW, the contents of the flip-flops are available at the outputs.
When OE
is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE
input does not affect the state of the flip-flops.
Bus hold on data inputs eliminates the need for external pull-up resistors to hold unused
inputs.
To reduce line noise, 30 series termination resistors are included in both high and low
output stages.
2. Features and benefits
5 V tolerant inputs/outputs for interfacing with 5 V logic
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low power consumption
Multibyte flow-through standard pinout architecture
Multiple low inductance supply pins for minimum noise and ground bounce
Direct interface with TTL levels
All data inputs have bus hold
High-impedance outputs when V
CC
= 0 V
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-B exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Specified from 40 C to +85 C and 40 C to +125 C
74LVCH162374A
16-bit edge-triggered D-type flip-flop with 30 series
termination resistors; 5 V input/output tolerant; 3-state
Rev. 4 — 22 January 2013 Product data sheet
