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74LVCH162374ADGG,1

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18
74LVCH162374A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 4 — 22 January 2013 3 of 17
NXP Semiconductors
74LVCH162374A
16-bit edge-triggered D-type flip-flop; 30 resistors; 3-state
Fig 3. Logic diagram
001aaa255
1CP
1OE
to 7 other channels
D
CP
Q
FF1
1Q01D0
2CP
2OE
to 7 other channels
D
CP
Q
FF2
2Q02D0
Fig 4. Bus hold circuit
to internal circuit
mgu771
V
CC
data input
74LVCH162374A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 4 — 22 January 2013 4 of 17
NXP Semiconductors
74LVCH162374A
16-bit edge-triggered D-type flip-flop; 30 resistors; 3-state
5. Pinning information
5.1 Pinning
5.2 Pin description
Fig 5. Pin configuration SSOP48 and TSSOP48
Table 2. Pin description
Symbol Pin Description
1OE
1 output enable input (active LOW)
2OE
24 output enable input (active LOW)
1CP 48 clock input
2CP 25 clock input
GND 4, 10, 15, 21, 28, 34, 39, 45 ground (0 V)
V
CC
7, 18, 31, 42 supply voltage
1Q[0:7] 2, 3, 5, 6, 8, 9, 11, 12 data output
2Q[0:7] 13, 14, 16, 17, 19, 20, 22, 23 data output
1D[0:7] 47, 46, 44, 43, 41, 40, 38, 37 data input
2D[0:7] 36, 35, 33, 32, 30, 29, 27, 26 data input
74LVCH162374A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 4 — 22 January 2013 5 of 17
NXP Semiconductors
74LVCH162374A
16-bit edge-triggered D-type flip-flop; 30 resistors; 3-state
6. Functional description
[1] H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the HIGH to LOW LE transition
L = LOW voltage level
l = LOW voltage level one set-up time prior to the HIGH to LOW LE transition
Z = high-impedance OFF-state
= LOW to HIGH CP transition
7. Limiting values
[1] The minimum input voltage ratings may be exceeded if the input current ratings are observed.
[2] The output voltage ratings may be exceeded if the output current ratings are observed.
[3] Above 60 C, the value of P
tot
derates linearly with 5.5 mW/K.
Table 3. Function selection
[1]
Operation modes Input Internal
flip-flop
Output
nOE nCP nD0 to nD7 nQ0 to nQ7
Load and read register L lLL
L hHH
Latch register and disable outputs H lLZ
H hHZ
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
V
CC
supply voltage 0.5 +6.5 V
I
IK
input clamping current V
I
< 0 V 50 - mA
V
I
input voltage
[1]
0.5 +6.5 V
I
OK
output clamping current V
O
> V
CC
or V
O
< 0 V - 50 mA
V
O
output voltage output HIGH or LOW state
[2]
0.5 V
CC
+ 0.5 V
output 3-state
[2]
0.5 +6.5 V
I
O
output current V
O
= 0 V to V
CC
- 50 mA
I
CC
supply current - 100 mA
I
GND
ground current 100 - mA
T
stg
storage temperature 65 +150 C
P
tot
total power dissipation T
amb
= 40 C to +125 C
[3]
- 500 mW
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18

74LVCH162374ADGG,1

Mfr. #:
Buy 74LVCH162374ADGG,1
Manufacturer:
Nexperia
Description:
Flip Flops 16b EDGE TRIG DTYPE FLIP FLOP 5V IN/OUT
Lifecycle:
New from this manufacturer.
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