P89LPC932A1_3 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 03 — 12 March 2007 2 of 64
NXP Semiconductors
P89LPC932A1
8-bit microcontroller with accelerated two-clock 80C51 core
n In-Circuit Programming (ICP) allows simple production coding with commercial
EPROM programmers. Flash security bits prevent reading of sensitive application
programs.
n Serial flash In-System Programming (ISP) allows coding while the device is mounted
in the end application.
n In-Application Programming (IAP) of the flash code memory. This allows changing the
code in a running application.
n Watchdog timer with separate on-chip oscillator, requiring no external components.
The watchdog prescaler is selectable from eight values.
n Low voltage reset (brownout detect) allows a graceful system shutdown when power
fails. May optionally be configured as an interrupt.
n Idle and two different power-down reduced power modes. Improved wake-up from
Power-down mode (a LOW interrupt input starts execution). Typical power-down
current is 1 µA (total power-down with voltage comparators disabled).
n Active-LOW reset. On-chip power-on reset allows operation without external reset
components. A reset counter and reset glitch suppression circuitry prevent spurious
and incomplete resets. A software reset function is also available.
n Configurable on-chip oscillator with frequency range options selected by user
programmed flash configuration bits. Oscillator options support frequencies from
20 kHz to the maximum operating frequency of 18 MHz.
n Oscillator fail detect. The watchdog timer has a separate fully on-chip oscillator
allowing it to perform an oscillator fail detect function.
n Programmable port output configuration options: quasi-bidirectional, open drain,
push-pull, input-only.
n Port ‘input pattern match’ detect. Port 0 may generate an interrupt when the value of
the pins match or do not match a programmable pattern.
n LED drive capability (20 mA) on all port pins. A maximum limit is specified for the
entire chip.
n Controlled slew rate port outputs to reduce EMI. Outputs have approximately 10 ns
minimum ramp times.
n Only power and ground connections are required to operate the P89LPC932A1 when
internal reset option is selected.
n Four interrupt priority levels.
n Eight keypad interrupt inputs, plus two additional external interrupt inputs.
n Schmitt trigger port inputs.
n Second data pointer.
n Emulation support.
2.3 Comparison to the P89LPC932
The P89LPC932A1 includes several improvements compared to the P89LPC932. Please
see
P89LPC932A1 User manual
for additional detailed information.
n Byte-erasability has been added to the user code memory space.
n All of the errata described in the P89LPC932 Errata sheet have been fixed.
n Serial ICP has been added.
