P89LPC932A1_3 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 03 — 12 March 2007 30 of 64
NXP Semiconductors
P89LPC932A1
8-bit microcontroller with accelerated two-clock 80C51 core
7.19.9 CCU interrupts
There are seven interrupt sources on the CCU which share a common interrupt vector.
7.20 UART
The P89LPC932A1 has an enhanced UART that is compatible with the conventional
80C51 UART except that Timer 2 overflow cannot be used as a baud rate source. The
P89LPC932A1 does include an independent Baud Rate Generator. The baud rate can be
selected from the oscillator (divided by a constant), Timer 1 overflow, or the independent
Baud Rate Generator. In addition to the baud rate generation, enhancements over the
standard 80C51 UART include Framing Error detection, automatic address recognition,
selectable double buffering and several interrupt options. The UART can be operated in
four modes: shift register, 8-bit UART, 9-bit UART, and CPU clock/32 or CPU clock/16.
7.20.1 Mode 0
Serial data enters and exits through RXD. TXD outputs the shift clock. 8 bits are
transmitted or received, LSB first. The baud rate is fixed at
1
⁄
16
of the CPU clock
frequency.
7.20.2 Mode 1
10 bits are transmitted (through TXD) or received (through RXD): a start bit (logic 0),
8 data bits (LSB first), and a stop bit (logic 1). When data is received, the stop bit is stored
in RB8 in Special Function Register SCON. The baud rate is variable and is determined
by the Timer 1 overflow rate or the Baud Rate Generator (described in Section 7.20.5
“Baud rate generator and selection”).
Fig 12. Capture/compare unit interrupts
002aaa896
interrupt to
CPU
TOIE2 (TICR2.7)
TOIF2 (TIFR2.7)
TICIE2A (TICR2.0)
TICF2A (TIFR2.0)
TICIE2B (TICR2.1)
TICF2B (TIFR2.1)
TOCIE2A (TICR2.3)
TOCF2A (TIFR2.3)
TOCIE2B (TICR2.4)
TOCF2B (TIFR2.4)
TOCIE2C (TICR2.5)
TOCF2C (TIFR2.5)
TOCIE2D (TICR2.6)
TOCF2D (TIFR2.6)
EA (IEN0.7)
ECCU (IEN1.4)
PRIORITY
ENCODER
other
interrupt
sources
ENCINT.0
ENCINT.1
ENCINT.2
