P89LPC932A1FA,112

[1] BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is logic 0. If any are written while BRGEN = 1, the result is unpredictable.

[2] All ports are in input only (high-impedance) state after power-up.

[3] The RSTSRC register reflects the cause of the P89LPC932A1 reset. Upon a power-up reset, all reset source flags are cleared except POF and BOF; the power-on reset value is

xx11 0000.

[4] The only reset source that affects these SFRs is power-on reset.

P89LPC932A1_3 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 03 — 12 March 2007 17 of 64

instructions execute in one or two machine cycles.

7.3 Clocks

The P89LPC932A1 device has several internal clocks as defined below:

OSCCLK — Input to the DIVM clock divider. OSCCLK is selected from one of four clock

sources (see Figure 7) and can also be optionally divided to a slower frequency (see

Section 7.8 “CCLK modification: DIVM register”).

Note: f

is defined as the OSCCLK frequency.

CCLK — CPU clock; output of the clock divider. There are two CCLK cycles per machine

The P89LPC932A1 provides several user-selectable oscillator options in generating the

CPU clock. This allows optimization for a range of needs from high precision to lowest

possible cost. These options are configured when the flash is programmed and include an

on-chip watchdog oscillator, an on-chip RC oscillator, an oscillator using an external

crystal, or an external clock source. The crystal oscillator can be optimized for low,

medium, or high frequency crystals covering a range from 20 kHz to 18 MHz.

This option supports an external crystal in the range of 20 kHz to 100 kHz. Ceramic

resonators are also supported in this configuration.

The P89LPC932A1 supports a user-selectable clock output function on the

XTAL2/CLKOUT pin when crystal oscillator is not being used. This condition occurs if

another clock source has been selected (on-chip RC oscillator, watchdog oscillator,

external clock input on X1) and if the RTC is not using the crystal oscillator as its clock

source. This allows external devices to synchronize to the P89LPC932A1. This output is

enabled by the ENCLK bit in the TRIM register.

P89LPC932A1_3 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 03 — 12 March 2007 18 of 64

7.4 On-chip RC oscillator option

The watchdog has a separate oscillator which has a frequency of 400 kHz. This oscillator

can be used to save power when a high clock frequency is not needed.

7.6 External clock input option

In this configuration, the processor clock is derived from an external source driving the

P3.1/XTAL1 pin. The rate may be from 0 Hz up to 18 MHz. The P3.0/XTAL2 pin may be

used as a standard port pin or a clock output. When using an oscillator frequency