P89LPC932A1_3 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 03 — 12 March 2007 50 of 64
NXP Semiconductors
P89LPC932A1
8-bit microcontroller with accelerated two-clock 80C51 core
Table 10. Dynamic characteristics (18 MHz)
V
DD
= 3.0 V to 3.6 V unless otherwise specified.
T
amb
=
−
40
°
C to +85
°
C for industrial applications, unless otherwise specified.
[1][2]
Symbol Parameter Conditions Variable clock f
osc
=18MHz Unit
Min Max Min Max
f
OSC(RC)
internal RC oscillator frequency 7.189 7.557 7.189 7.557 MHz
f
OSC(WD)
internal watchdog oscillator
frequency
280 480 280 480 kHz
f
osc
oscillator frequency 0 18 - - MHz
T
cy(CLK)
clock cycle time see Figure 23 55 - - - ns
f
CLKLP
low power select clock frequency 0 8 - - MHz
Glitch filter
t
gr
glitch rejection P1.5/RST pin - 50 - 50 ns
any pin except
P1.5/
RST
- 15 - 15 ns
t
sa
signal acceptance P1.5/RST pin 125 - 125 - ns
any pin except
P1.5/
RST
50 - 50 - ns
External clock
t
CHCX
clock HIGH time see Figure 23 22 T
cy(CLK)
− t
CLCX
22 - ns
t
CLCX
clock LOW time see Figure 23 22 T
cy(CLK)
− t
CHCX
22 - ns
t
CLCH
clock rise time see Figure 23 -5-5ns
t
CHCL
clock fall time see Figure 23 -5-5ns
Shift register (UART mode 0)
t
XLXL
serial port clock cycle time see Figure 22 16T
cy(CLK)
- 888 - ns
t
QVXH
output data set-up to clock rising
edge time
see Figure 22 13T
cy(CLK)
- 722 - ns
t
XHQX
output data hold after clock rising
edge time
see Figure 22 -T
cy(CLK)
+ 20 - 75 ns
t
XHDX
input data hold after clock rising
edge time
see Figure 22 -0-0ns
t
XHDV
input data valid to clock rising
edge time
see Figure 22 150 - 150 - ns
SPI interface
f
SPI
SPI operating frequency
slave 0 CCLK⁄6 0 3.0 MHz
master - CCLK⁄4 - 4.5 MHz
T
SPICYC
SPI cycle time see Figure 24,
25, 26, 27
slave 6⁄CCLK - 333 - ns
master 4⁄CCLK - 222 - ns
t
SPILEAD
SPI enable lead time see Figure 26, 27
2.0 MHz (slave) 250 - 250 - ns
t
SPILAG
SPI enable lag time see Figure 26, 27
2.0 MHz (slave) 250 - 250 - ns
