P89LPC932A1_3 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 03 — 12 March 2007 54 of 64
NXP Semiconductors
P89LPC932A1
8-bit microcontroller with accelerated two-clock 80C51 core
10.2 ISP entry mode
Fig 27. SPI slave timing (CPHA = 1)
002aaa911
T
SPICYC
t
SPICLKH
t
SPICLKH
t
SPICLKL
t
SPILEAD
t
SPICLKL
t
SPILAG
t
SPIDSU
t
SPIDSU
t
SPIDSU
t
SPIDH
t
SPIDH
t
SPIR
t
SPIR
t
SPIR
t
SPIA
t
SPIOH
t
SPIOH
t
SPIOH
t
SPIDIS
slave MSB/LSB out
not defined
MSB/LSB in LSB/MSB in
slave LSB/MSB out
t
SPIDV
t
SPIDV
t
SPIDV
t
SPIR
t
SPIF
t
SPIF
SS
SPICLK
(CPOL = 0)
(input)
SPICLK
(CPOL = 1)
(input)
MISO
(output)
MOSI
(input)
Table 11. Dynamic characteristics, ISP entry mode
V
DD
= 2.4 V to 3.6 V, unless otherwise specified.
T
amb
=
−
40
°
C to +85
°
C for industrial applications, unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
t
VR
V
DD
active to RST active delay time 50 - - µs
t
RH
RST HIGH time 1 - 32 µs
t
RL
RST LOW time 1 - - µs
Fig 28. ISP entry waveform
002aaa912
V
DD
RST
t
RL
t
VR
t
RH
