74AHC_AHCT595_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 12 July 2012 13 of 22
NXP Semiconductors
74AHC595-Q100; 74AHCT595-Q100
8-bit serial-in/serial-out or parallel-out shift register with output latches
Measurement points are given in Table 8.
The shaded areas indicate when the input is permitted to change for predictable output performance.
V
OL
and V
OH
are typical output voltage levels that occur with the output load.
Fig 10. Data set-up and hold times
mna560
GND
GND
t
h
t
su
t
h
t
su
V
M
V
M
V
M
V
I
V
OH
V
OL
V
I
Q7S output
SH
CP input
D
S input
Measurement points are given in Table 8.
V
OL
and V
OH
are typical output voltage levels that occur with the output load.
Fig 11. Master reset to output propagation delays
mna561
MR
input
SH
CP input
Q
7S output
t
PHL
t
W
t
rec
V
M
V
OH
V
OL
V
I
GND
V
I
GND
V
M
V
M
