74AHC_AHCT595_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 12 July 2012 4 of 22
NXP Semiconductors
74AHC595-Q100; 74AHCT595-Q100
8-bit serial-in/serial-out or parallel-out shift register with output latches
6. Pinning information
6.1 Pinning
6.2 Pin description
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 5. Pin configuration SO16 and TSSOP16 Fig 6. Pin configuration DHVQFN16
$+&4
$+&74
49
&&
44
4
'6
4
2(
4
67&3
4
6+&3
4
05
*1'
46
DDD
4 2(
4 '6
4 4
*1'
46
4
9
&&
Table 2. Pin description
Symbol Pin Description
Q1 1 parallel data output 1
Q2 2 parallel data output 2
Q3 3 parallel data output 3
Q4 4 parallel data output 4
Q5 5 parallel data output 5
Q6 6 parallel data output 6
Q7 7 parallel data output 7
GND 8 ground (0 V)
Q7S 9 serial data output
MR
10 master reset (active LOW)
SHCP 11 shift register clock input
STCP 12 storage register clock input
OE
13 output enable input (active LOW)
DS 14 serial data input
Q0 15 parallel data output 0
V
CC
16 supply voltage
