74AHC_AHCT595_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 12 July 2012 15 of 22
NXP Semiconductors
74AHC595-Q100; 74AHCT595-Q100
8-bit serial-in/serial-out or parallel-out shift register with output latches
Test data is given in Table 9.
Definitions for test circuit:
C
L
= load capacitance including jig and probe capacitance.
R
L
= load resistance.
R
T
= termination resistance should be equal to the output impedance Z
o
of the pulse generator.
S1 = test selection switch.
Fig 13. Load circuitry for switching times
V
M
V
M
t
W
t
W
10 %
90 %
0 V
V
I
V
I
negative
pulse
positive
pulse
0 V
V
M
V
M
90 %
10 %
t
f
t
r
t
r
t
f
001aad983
DUT
V
CC
V
CC
V
I
V
O
R
T
R
L
S1
C
L
open
G
Table 9. Test data
Type Input Load S1 position
V
I
t
r
, t
f
C
L
R
L
t
PHL
, t
PLH
t
PZH
, t
PHZ
t
PZL
, t
PLZ
74AHC595-Q100 V
CC
3.0ns 15pF, 50pF 1k open GND V
CC
74AHCT595-Q100 3.0 V 3.0ns 15pF, 50pF 1k open GND V
CC
