MC74HC165ADTR2G

© Semiconductor Components Industries, LLC, 2014
October, 2014 − Rev. 9
1 Publication Order Number:
MC74HC165A/D
MC74HC165A
8-Bit Serial or
Parallel-Input/
Serial-Output Shift Register
High−Performance Silicon−Gate CMOS
The MC74HC165A is identical in pinout to the LS165. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
This device is an 8−bit shift register with complementary outputs
from the last stage. Data may be loaded into the register either in
parallel or in serial form. When the Serial Shift/Parallel Load
input is
low, the data is loaded asynchronously in parallel. When the Serial
Shift/Parallel Load
input is high, the data is loaded serially on the
rising edge of either Clock or Clock Inhibit (see the Function Table).
The 2−input NOR clock may be used either by combining two
independent clock sources or by designating one of the clock inputs to
act as a clock inhibit.
Features
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1 mA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7 A
Chip Complexity: 286 FETs or 71.5 Equivalent Gates
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
These Devices are Pb−Free, Halogen Free and are RoHS Compliant
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
ORDERING INFORMATION
MARKING
DIAGRAMS
SOIC−16
D SUFFIX
CASE 751B
TSSOP−16
DT SUFFIX
CASE 948F
1
1
6
PDIP−16
N SUFFIX
CASE 648
1
16
1
16
1
16
MC74HC165AN
AWLYYWWG
1
16
HC165AG
AWLYWW
HC
165A
ALYWG
G
1
16
A = Assembly Lo-
cation
L, WL = Wafer Lot
Y, YY = Year
W, WW = Work Week
G or G = Pb−Free Package
(Note: Microdot may be in either location)
165A
ALYWG
G
QFN16
MN SUFFIX
CASE 485AW
1
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MC74HC165A
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2
PIN 16 = V
CC
PIN 8 = GND
11
12
13
14
3
4
5
6
10
A
B
C
D
E
F
G
H
S
A
PARALLEL
DATA
INPUTS
SERIAL
DATA
INPUT
SERIAL SHIFT/
PARALLEL LOAD
1
2
15
CLOCK
CLOCK INHIBIT
9
7
Q
H
Q
H
SERIAL
DATA
OUTPUTS
Figure 1. Pin Assignments
13
14
15
16
9
10
11
125
4
3
2
1
8
7
6
B
C
D
CLOCK INHIBIT
V
CC
Q
H
S
A
A
F
E
CLOCK
SERIAL SHIFT/
PARALLEL LOAD
GND
Q
H
H
G
Figure 2. Logic Diagram
116
215
314
413
512
611
710
89
GND
B
C
D
CLOCK INHIBIT
V
CC
Q
H
S
A
A
F
E
CLOCK
SERIAL SHIFT/
PARALLEL LOAD
GND
Q
H
H
G
FUNCTION TABLE
Inputs Internal Stages Output
Operation
Serial Shift/
Parallel Load
Clock
Clock
Inhibit
S
A
A − H Q
A
Q
B
Q
H
L X X X a h a b h Asynchronous Parallel Load
H
H
L
L
L
H
X
X
L
H
Q
An
Q
An
Q
Gn
Q
Gn
Serial Shift via Clock
H
H
L
L
L
H
X
X
L
H
Q
An
Q
An
Q
Gn
Q
Gn
Serial Shift via Clock Inhibit
H
H
X
H
H
X
X
X
X
X
No Change Inhibited Clock
H L L X X No Change No Clock
X = don’t care Q
An
− Q
Gn
= Data shifted from the preceding stage
MC74HC165A
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3
MAXIMUM RATINGS
Symbol Parameter Value Unit
V
CC
DC Supply Voltage (Referenced to GND) – 0.5 to + 7.0 V
V
in
DC Input Voltage (Referenced to GND) – 0.5 to V
CC
+ 0.5 V
V
out
DC Output Voltage (Referenced to GND) – 0.5 to V
CC
+ 0.5 V
I
in
DC Input Current, per Pin ± 20 mA
I
out
DC Output Current, per Pin ± 25 mA
I
CC
DC Supply Current, V
CC
and GND Pins ± 50 mA
P
D
Power Dissipation in Still Air Plastic DIP†
SOIC Package†
TSSOP Package†
750
500
450
mW
T
stg
Storage Temperature – 65 to + 150
_C
T
L
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP, SOIC or TSSOP Package)
260
_C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of
these limits are exceeded, device functionality should not be assumed, damage may occur and
reliability may be affected.
Derating Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: − 6.1 mW/_C from 65_ to 125_C
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
V
CC
DC Supply Voltage (Referenced to GND) 2.0 6.0 V
V
in
, V
out
DC Input Voltage, Output Voltage (Referenced to
GND)
0 V
CC
V
T
A
Operating Temperature, All Package Types – 55 + 125
_C
t
r
, t
f
Input Rise and Fall Time V
CC
= 2.0 V
(Figure 1) V
CC
= 3.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
0
0
0
1000
600
500
400
ns
Functional operation above the stresses listed in the Recommended Operating Ranges is not
implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may
affect device reliability.
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Symbo
l
Parameter Test Conditions
V
CC
V
Guaranteed Limit
Unit
– 55 to 25_C v 85_C v 125_C
V
IH
Minimum High−Level Input
Voltage
V
out
= 0.1 V or V
CC
– 0.1 V
|I
out
| v 20 mA
2.0
3.0
4.5
6.0
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
V
V
IL
Maximum Low−Level Input
Voltage
V
out
= 0.1 V or V
CC
– 0.1 V
|I
out
| v 20 mA
2.0
3.0
4.5
6.0
0.5
0.9
1.35
1.80
0.5
0.9
1.35
1.80
0.5
0.9
1.35
1.80
V
V
OH
Minimum High−Level Output
Voltage
V
in
= V
IH
or V
IL
|I
out
| v 20 mA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
in
= V
IH
or V
IL
|I
out
| v 2.4 mA
|I
out
| v 4.0 mA
|I
out
| v 5.2 mA
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.20
3.70
5.20
V
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
cuit. For proper operation, V
in
and
V
out
should be constrained to the
range GND v (V
in
or V
out
) v V
CC
.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V
CC
).
Unused outputs must be left open.

MC74HC165ADTR2G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Counter Shift Registers 8bit Serial/Parallel In Serial Out
Lifecycle:
New from this manufacturer.
Delivery:
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