OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

MC74HC165ADTR2G

P1-P3P4-P6P7-P9P10-P12
MC74HC165A
www.onsemi.com
4
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Symbol Unit
Guaranteed Limit
V
CC
V
Test ConditionsParameter
Symbol Unit
v 125_Cv 85_C– 55 to 25_C
V
CC
V
Test ConditionsParameter
V
OL
Maximum Low−Level Output
Voltage
V
in
= V
IH
or V
IL
|I
out
| v 20 mA
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
in
= V
IH
or V
IL
|I
out
| v 2.4 mA
|I
out
| v 4.0 mA
|I
out
| v 5.2 mA
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.40
0.40
0.40
I
in
Maximum Input Leakage
Current
V
in
= V
CC
or GND 6.0 ± 0.1 ± 1.0 ± 1.0
mA
I
CC
Maximum Quiescent Supply
Current (per Package)
V
in
= V
CC
or GND
I
out
= 0 mA
6.0 4 40 160
mA
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
AC ELECTRICAL CHARACTERISTICS (C
L
= 50 pF, Input t
r
= t
f
= 6 ns)
Symbo
l
Parameter
V
CC
V
Guaranteed Limit
Unit
– 55 to 25_C v 85_C v 125_C
f
max
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 8)
2.0
3.0
4.5
6.0
6
18
30
35
4.8
17
24
28
4
15
20
24
MHz
t
PLH
,
t
PHL
Maximum Propagation Delay, Clock (or Clock Inhibit) to Q
H
or Q
H
(Figures 1 and 8)
2.0
3.0
4.5
6.0
150
52
30
26
190
63
38
33
225
65
45
38
ns
t
PLH
,
t
PHL
Maximum Propagation Delay, Serial Shift/Parallel Load to Q
H
or Q
H
(Figures 2 and 8)
2.0
3.0
4.5
6.0
175
58
35
30
220
70
44
37
265
72
53
45
ns
t
PLH
,
t
PHL
Maximum Propagation Delay, Input H to Q
H
or Q
H
(Figures 3 and 8)
2.0
3.0
4.5
6.0
150
52
30
26
190
63
38
33
225
65
45
38
ns
t
TLH
,
t
THL
Maximum Output Transition Time, Any Output
(Figures 1 and 8)
2.0
3.0
4.5
6.0
75
27
15
13
95
32
19
16
110
36
22
19
ns
C
in
Maximum Input Capacitance − 10 10 10 pF
C
PD
Power Dissipation Capacitance (Per Package)*
Typical @ 25°C, V
CC
= 5.0 V
pF
40
* Used to determine the no−load dynamic power consumption: P
D
= C
PD
V
CC
2
f + I
CC
V
CC
.
MC74HC165A
www.onsemi.com
5
TIMING REQUIREMENTS (Input t
r
= t
f
= 6 ns)
Symbo
l
Parameter
V
CC
V
Guaranteed Limit
Unit
– 55 to 25_C v 85_C v 125_C
t
su
Minimum Setup Time, Parallel Data Inputs to Serial Shift/Parallel Load
(Figure 4)
2.0
3.0
4.5
6.0
75
30
15
13
95
40
19
16
110
55
22
19
ns
t
su
Minimum Setup Time, Input SA to Clock (or Clock Inhibit)
(Figure 5)
2.0
3.0
4.5
6.0
75
30
15
13
95
40
19
16
110
55
22
19
ns
t
su
Minimum Setup Time, Serial Shift/Parallel Load to Clock (or Clock Inhibit)
(Figure 6)
2.0
3.0
4.5
6.0
75
30
15
13
95
40
19
16
110
55
22
19
ns
t
su
Minimum Setup Time, Clock to Clock Inhibit
(Figure 7)
2.0
3.0
4.5
6.0
75
30
15
13
95
40
19
16
110
55
22
19
ns
t
h
Minimum Hold Time, Serial Shift/Parallel Load to Parallel Data Inputs
(Figure 4)
2.0
3.0
4.5
6.0
5
5
5
5
5
5
5
5
5
5
5
5
ns
t
h
Minimum Hold Time, Clock (or Clock Inhibit) to Input SA
(Figure 5)
2.0
3.0
4.5
6.0
5
5
5
5
5
5
5
5
5
5
5
5
ns
t
h
Minimum Hold Time, Clock (or Clock Inhibit) to Serial Shift/Parallel Load
(Figure 6)
2.0
3.0
4.5
6.0
5
5
5
5
5
5
5
5
5
5
5
5
ns
t
rec
Minimum Recovery Time, Clock to Clock Inhibit
(Figure 7)
2.0
3.0
4.5
6.0
75
30
15
13
95
40
19
16
110
55
22
19
ns
t
w
Minimum Pulse Width, Clock (or Clock Inhibit)
(Figure 1)
2.0
3.0
4.5
6.0
70
27
15
13
90
32
19
16
100
36
22
19
ns
t
w
Minimum Pulse width, Serial Shift/Parallel Load
(Figure 2)
2.0
3.0
4.5
6.0
70
27
15
13
90
32
19
16
100
36
22
19
ns
t
r
, t
f
Maximum Input Rise and Fall Times
(Figure 1)
2.0
3.0
4.5
6.0
1000
800
500
400
1000
800
500
400
1000
800
500
400
ns
MC74HC165A
www.onsemi.com
6
PIN DESCRIPTIONS
INPUTS
A, B, C, D, E, F, G, H (Pins 11, 12, 13, 14, 3, 4, 5, 6)
Parallel Data inputs. Data on these inputs are
asynchronously entered in parallel into the internal
flip−flops when the Serial Shift/Parallel Load
input is low.
SA (Pin 10)
Serial Data input. When the Serial Shift/Parallel Load
input is high, data on this pin is serially entered into the first
stage of the shift register with the rising edge of the Clock.
CONTROL INPUTS
Serial Shift/Parallel Load
(Pin 1)
Data−entry control input. When a high level is applied to
this pin, data at the Serial Data input (SA) are shifted into the
register with the rising edge of the Clock. When a low level
is applied to this pin, data at the Parallel Data inputs are
asynchronously loaded into each of the eight internal stages.
Clock, Clock Inhibit (Pins 2, 15)
Clock inputs. These two clock inputs function identically.
Either may be used as an active−high clock inhibit.
However, to avoid double clocking, the inhibit input should
go high only while the clock input is high.
The shift register is completely static, allowing Clock
rates down to DC in a continuous or intermittent mode.
OUTPUTS
Q
H
, Q
H
(Pins 9, 7)
Complementary Shift Register outputs. These pins are the
noninverted and inverted outputs of the eighth stage of the
shift register.
ORDERING INFORMATION
Device Package Shipping
†
MC74HC165ANG PDIP−16
(Pb−Free)
500 Units / Rail
MC74HC165ADG SOIC−16
(Pb−Free)
48 Units / Rail
MC74HC165ADR2G SOIC−16
(Pb−Free)
2500 Units / Reel
NLV74HC165ADR2G* SOIC−16
(Pb−Free)
2500 Units / Reel
MC74HC165ADTR2G TSSOP−16
(Pb−Free)
2500 Units / Reel
NLV74HC165ADTR2G* TSSOP−16
(Pb−Free)
2500 Units / Reel
MC74HC165AMNTWG QFN16
(Pb−Free)
3000 Units / Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.
P1-P3P4-P6P7-P9P10-P12

MC74HC165ADTR2G

Mfr. #:
Buy MC74HC165ADTR2G
Manufacturer:
ON Semiconductor
Description:
Counter Shift Registers 8bit Serial/Parallel In Serial Out
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet