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MC74HC165ADTR2G

P1-P3P4-P6P7-P9P10-P12
MC74HC165A
www.onsemi.com
7
SWITCHING WAVEFORMS
t
r
t
f
V
CC
GND
90%
50%
10%
t
PLH
t
PHL
CLOCK
OR CLOCK INHIBIT
90%
50%
10%
t
TLH
t
THL
Q
H
OR Q
H
SERIAL SHIFT/
PARALLEL LOAD
Q
H
OR Q
H
50%
t
PLH
50%
V
CC
GND
t
PHL
50%
t
r
t
f
INPUT H
90%
50%
10%
90%
50%
10%
V
CC
GND
t
PHL
t
THL
t
TLH
t
PLH
Q
H
OR Q
H
50%
V
CC
GND
t
h
V
CC
GND
ASYNCHRONOUS PARALLEL
LOAD
(LEVEL SENSITIVE)
SERIAL SHIFT/
PARALLEL LOAD
INPUTS A-H
INPUT S
A
50%
50%
CLOCK
OR CLOCK INHIBIT
V
CC
GND
V
CC
GND
SERIAL SHIFT/
PARALLEL LOAD
CLOCK
OR CLOCK INHIBIT
50%
50%
t
su
V
CC
GND
V
CC
GND
CLOCK 2 INHIBITED
CLOCK INHIBIT
CLOCK
50%
50%
t
su
t
rec
V
CC
GND
V
CC
GND
*Includes all probe and jig capacitance
C
L
*
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
t
w
1/f
max
t
w
VALID
t
su
VALID
t
su
t
h
t
h
Figure 3. Serial−Shirt Mode Figure 4. Parallel−Load Mode
Figure 5. Parallel−Load Mode Figure 6. Parallel−Load Mode
Figure 7. Serial−Shift Mode Figure 8. Serial−Shift Mode
Figure 9. Serial−Shift, Clock−Inhibit Mode Figure 10. Test Circuit
MC74HC165A
www.onsemi.com
8
ABC FGH
11 12 13 4 5 6
9
Q
H
7
Q
H
SERIAL SHIFT/
PARALLEL LOAD
1
SERIAL DATA
INPUT S
A
10
CLOCK
2
CLOCK
INHIBIT
15
EXPANDED LOGIC DIAGRAM
CLOCK
CLOCK INHIBIT
S
A
SERIAL SHIFT/
PARALLEL LOAD
A
B
C
D
E
F
G
H
Q
H
Q
H
H
L
H
L
H
L
H
H
HH
LL
L
H
H
L
L
H
H
L
L
H
H
L
PARALLEL LOAD
PARALLEL
DATA
INPUTS
TIMING DIAGRAM
DQ
A
CC
DQ
B
CC
DQ
C
CC
DQ
F
CC
DQ
G
CC
DQ
H
CC
CLOCK
INHIBIT
MODE
SERIAL-SHIFT MODE
MC74HC165A
www.onsemi.com
9
PACKAGE DIMENSIONS
PDIP−16
CASE 648−08
ISSUE U
18
16 9
b2
NOTE 8
D
A
TOP VIEW
E1
B
b
L
A1
A
C
SEATING
PLANE
0.010 CA
SIDE VIEW
M
16X
D1
e
A2
NOTE 3
M
B
M
eB
E
END VIEW
END VIEW
WITH LEADS CONSTRAINED
DIM MIN MAX
INCHES
A −−−− 0.210
A1 0.015 −−−−
b 0.014 0.022
C 0.008 0.014
D 0.735 0.775
D1 0.005 −−−−
e 0.100 BSC
E 0.300 0.325
M −−−− 10
−−− 5.33
0.38 −−−
0.35 0.56
0.20 0.36
18.67 19.69
0.13 −−−
2.54 BSC
7.62 8.26
−−− 10
MIN MAX
MILLIMETERS
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. DIMENSIONS A, A1 AND L ARE MEASURED WITH THE PACK-
AGE SEATED IN JEDEC SEATING PLANE GAUGE GS−3.
4. DIMENSIONS D, D1 AND E1 DO NOT INCLUDE MOLD FLASH
OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS ARE
NOT TO EXCEED 0.10 INCH.
5. DIMENSION E IS MEASURED AT A POINT 0.015 BELOW DATUM
PLANE H WITH THE LEADS CONSTRAINED PERPENDICULAR
TO DATUM C.
6. DIMENSION E3 IS MEASURED AT THE LEAD TIPS WITH THE
LEADS UNCONSTRAINED.
7. DATUM PLANE H IS COINCIDENT WITH THE BOTTOM OF THE
LEADS, WHERE THE LEADS EXIT THE BODY.
8. PACKAGE CONTOUR IS OPTIONAL (ROUNDED OR SQUARE
CORNERS).
E1 0.240 0.280 6.10 7.11
b2
eB −−−− 0.430 −−− 10.92
0.060 TYP 1.52 TYP
c
A2 0.115 0.195 2.92 4.95
L 0.115 0.150 2.92 3.81
°°
H
NOTE 5
NOTE 6
M
e/2
P1-P3P4-P6P7-P9P10-P12

MC74HC165ADTR2G

Mfr. #:
Buy MC74HC165ADTR2G
Manufacturer:
ON Semiconductor
Description:
Counter Shift Registers 8bit Serial/Parallel In Serial Out
Lifecycle:
New from this manufacturer.
Delivery:
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