Document Number: 70071
S-71241–Rev. H, 25-Jun-07
www.vishay.com
7
Vishay Siliconix
DG884
TIMING DIAGRAMS
Figure 1. Input Timing Requirements
t
SW
t
AW
Presetting Device A
CS
for
Device A
CS
for
Device B
Address
B
0
B
1
Address
A
0
A
3
WR
SALVO
RS
I/O
Select Output 1
Presetting Device B
Donít Care
Donít Care
Select Output 2 Output N
Select Input Select Input Input
Reset Occuring at Any Time Results In All Current Event Latches Being Cleared
t
WA
t
WA
t
AW
t
WA
t
WP
t
SP
t
RS
t
CW
t
CA
t
IA
t
WS
t
AW
t
WC
t
SP
t
SW
t
CW
t
WS
Input
Figure 2. Output Timing Requirements
PARAMETER DEFINITIONS
Symbol Parameter Description
T
AW
Address to Write Minimum time address must be valid before WR
goes high
T
WA
Write to Address Minimum time address must remain valid after WR pulse goes high
T
WP
WR
Pulse Minimum time of WR pulse width to write address into Next Event latches
T
CW
Chip Select to WR
Minimum time chip select must be valid before a WR pulse
T
WC
WR
to Chip Select Minimum time chip select must remain valid after WR pulse
T
SP
SALVO Pulse Minimum time of SALVO pulse width
T
WS
WR
to SALVO Minimum time from WR pulse to SALVOto load new address
T
SW
SALVO
to WR Minimum time from SALVO pulse to WR to load current address
T
IA
I/O to Address In Minimum time I/O must be valid before address applied
T
RS
RS to SALVO Minimum time RS must be valid before SALVO pulse
T
IO
I/O to Output Minimum time I/O must be valid before address output valid
T
AO
Address to Output
Minimum time address B
X
must be valid until address A
X
output valid
T
CO
CS to Output
Minimum time CS
must be valid until A
X
output is valid
T
CA
CS
to Address In Minimum time CS must be valid before address applied if I/O is high
t
AO
t
AO
CS for
Device A
CS
for
Device B
Interrogating Device A
Address
B
0
B
1
Address
A
0
A
3
WR
SALVO
RS
I/O
Reset Occuring at Any Time Results In All Current Event Latches Being Cleared
t
IO
Select Current
Event Latch 1
Select Current
Event Latch
Interrogating Device B
Output
t
C
O
t
AO
Latch N
t
CA
Out N
t
C
O
t
C
A
t
AO
t
IA
Address Output 1
Address Output
