CY7C63001A-SC Datasheet CY7C63001A-PC, CY7C63001A-PXC, CY7C63001A-SC | P13-P15

CY7C63001

CY7C63101

Document #: 38-08026 Rev. *A Page 13 of 25

6.8.3 USB Interrupt

A USB Endpoint 0 interrupt is generated after the host has

written data to Endpoint 0 or after the USB Controller has

transmitted a packet from Endpoint 0 and receives an ACK

from the host. An OUT packet from the host which is NAKed

by the USB Controller does not generate an interrupt. This

interrupt is masked by the USB EP0 Interrupt Enable bit (bit 3)

of the Global Interrupt Enable Register.

A USB Endpoint 1 interrupt is generated after the USB

Controller has transmitted a packet from Endpoint 1 and has

received an ACK from the host. This interrupt is masked by the

USB EP1 Interrupt Enable bit (bit 4) of the Global Interrupt

Enable Register.

6.8.4 Timer Interrupt

There are two timer interrupts: the 128-µs interrupt and the

1.024-ms interrupt. They are masked by bits 1 and 2 of the

Global Interrupt Enable Register respectively. The user should

disable both timer interrupts before going into the suspend

mode to avoid possible conflicts from timer interrupts occurring

just as suspend mode is entered.

6.8.5 Wake-Up Interrupt

A wake-up interrupt is generated when the Cext pin goes

HIGH. This interrupt is latched in the interrupt controller. It can

be masked by the Wake-up Interrupt Enable bit (bit 7) of the

Global Interrupt Enable Register. This interrupt can be used to

perform periodic checks on attached peripherals when the

USB Controller is placed in the low-power suspend mode. See

the Instant-On Feature section for more details.

6.9 USB Engine

The USB engine includes the Serial Interface Engine (SIE)

and the low-speed USB I/O transceivers. The SIE block

performs most of the USB interface functions with only minimal

support from the microcontroller core. Two endpoints are

supported. Endpoint 0 is used to receive and transmit control

(including setup) packets while Endpoint 1 is only used to

transmit data packets.

The USB SIE processes USB bus activity at the transaction

level independently. It does all the NRZI encoding/decoding

and bit stuffing/unstuffing. It also determines token type,

checks address and endpoint values, generates and checks

CRC values, and controls the flow of data bytes between the

bus and the Endpoint FIFOs. NOTE: the SIE stalls the CPU for

three cycles per byte when writing data to the endpoint FIFOs

(or 3 * 1/12 MHz * 8 bytes = 2 µs per 8-byte transfer).

The firmware handles higher level and function-specific tasks.

During control transfers the firmware must interpret device

requests and respond correctly. It also must coordinate

Suspend/Resume, verify and select DATA toggle values, and

perform function specific tasks.

The USB engine and the firmware communicate though the

Endpoint FIFOs, USB Endpoint interrupts, and the USB

registers described in the sections below.

6.9.1 USB Enumeration Process

The USB Controller provides a USB Device Address Register

at I/O location 0x12. Reading and writing this register is

achieved via the IORD and IOWR instructions. The register

contents are cleared during a reset, setting the USB address

of the USB Controller to 0. Figure 6-20 shows the format of the

USB Address Register.

Typical enumeration steps:

1. The host computer sends a SETUP packet followed by a

DATA packet to USB address 0 requesting the Device

descriptor.

2. The USB Controller decodes the request and retrieves its

Device descriptor from the program memory space.

3. The host computer performs a control read sequence and

the USB Controller responds by sending the Device

descriptor over the USB bus.

4. After receiving the descriptor, the host computer sends a

SETUP packet followed by a DATA packet to address 0

assigning a new USB address to the device.

5. The USB Controller stores the new address in its USB

Device Address Register after the no-data control

sequence completes.

6. The host sends a request for the Device descriptor using

the new USB address.

7. The USB Controller decodes the request and retrieves the

Device descriptor from the program memory.

8. The host performs a control read sequence and the USB

Controller responds by sending its Device descriptor over

the USB bus.

9. The host generates control reads to the USB Controller to

request the Configuration and Report descriptors.

10.The USB Controller retrieves the descriptors from its

program space and returns the data to the host over the

USB.

11.Enumeration is complete after the host has received all the

descriptors.

b7 b6 b5 b4 b3 b2 b1 b0

Reserved ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0

R/W R/W R/W R/W R/W R/W R/W

00000000

Figure 6-20. USB Device Address Register (USB DA – Address 0x12)

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Document #: 38-08026 Rev. *A Page 14 of 25

6.9.2 Endpoint 0

All USB devices are required to have an endpoint number 0

that is used to initialize and manipulate the device. Endpoint 0

provides access to the device’s configuration information and

allows generic USB status and control accesses.

Endpoint 0 can receive and transmit data. Both receive and

transmit data share the same 8-byte Endpoint 0 FIFO located

at data memory space 0x70 to 0x77. Received data may

overwrite the data previously in the FIFO.

6.9.2.1 Endpoint 0 Receive

After receiving a packet and placing the data into the Endpoint

0 FIFO, the USB Controller updates the USB Endpoint 0 RX

Endpoint 0 interrupt. The format of the Endpoint 0 RX Register

is shown in Figure 6-21.

This is a read/write register located at I/O address 0x14. Any

write to this register clears all bits except bit 3 which remains

unchanged. All bits are cleared during reset.

Bit 0 is set to 1 when a SETUP token for Endpoint 0 is received.

Once set to a 1, this bit remains HIGH until it is cleared by an

I/O write or a reset. While the data following a SETUP is being

received by the USB engine, this bit is not cleared by an I/O

write. User firmware writes to the USB FIFOs are disabled

when bit 0 is set. This prevents SETUP data from being

overwritten.

Bits 1 and 2 are updated whenever a valid token is received

on Endpoint 0. Bit 1 is set to 1 if an OUT token is received and

cleared to 0 if any other token is received. Bit 2 is set to 1 if an

IN token is received and cleared to 0 if any other token is

received.

Bit 3 shows the Data Toggle status of DATA packets received

on Endpoint 0. This bit is updated for DATA following SETUP

tokens and for DATA following OUT tokens if Stall (bit 5 of

0x10) is not set and either EnableOuts or StatusOuts (bits 3

and 4 of 0x13) are set.

Bits 4 to 7 are the count of the number of bytes received in a

DATA packet. The two CRC bytes are included in the count,

so the count value is two greater than the number of data bytes

received. The count is always updated and the data is always

stored in the FIFO for DATA packets following a SETUP token.

The count for DATA following an OUT token is updated if Stall

(bit 5 of 0x10) is 0 and either EnableOuts or StatusOuts (bits

3 and 4 of 0x13) are 1. The DATA following an OUT is written

into the FIFO if EnableOuts is set to 1 and Stall and StatusOuts

are 0.

A maximum of eight bytes are written into the Endpoint 0 FIFO.

If there are less than eight bytes of data the CRC is written into

the FIFO.

Due to register space limitations, the Receive Data Invalid bit

is located in the USB Endpoint 0 TX Configuration Register.

Refer to the Endpoint 0 Transmit section for details. This bit is

set by the SIE if an error is detected in a received DATA packet.

Table 6-4 summarizes the USB Engine response to SETUP

and OUT transactions on Endpoint 0. In the Data Packet

column ‘Error’ represents a packet with a CRC, PID or bit-

stuffing error, or a packet with more than eight bytes of data.

‘Valid’ is a packet without an Error. ‘Status’ is a packet that is

a valid control read Status stage, while ‘N/Status’ is not a

correct Status stage (see section 6.9.4). The ‘Stall’ bit is

described in Section 6.9.2.2. The ‘StatusOuts’ and

‘EnableOuts’ bits are described in section 6.9.4.

b7 b6 b5 b4 b3 b2 b1 b0

COUNT3 COUNT2 COUNT1 COUNT0 TOGGLE IN OUT SETUP

R/W R/W R/W R/W R R/W R/W R/W

00000000

Figure 6-21. USB Endpoint 0 RX Register (Address 0x14)

Table 6-4. USB Engine Response to SETUP and OUT Transactions on Endpoint 0

Control Bit Settings Received Packets USB Engine Response

Stall Status Out Enable Out

Token

Type

Data

Packet FIFO Write

Toggle

Update

Count

Update Interrupt Reply

– – – SETUP Valid Yes Yes Yes Yes ACK

– – – SETUP Error Yes Yes Yes Yes None

0 0 1 OUT Valid Yes Yes Yes Yes ACK

0 0 1 OUT Error Yes Yes Yes Yes None

0 0 0OUTValidNoNoNoNoNAK

0 0 0OUTErrorNoNoNoNoNone

1 0 0OUTValidNoNoNoNoSTALL

1 0 0OUTErrorNoNoNoNoNone

0 1 0 OUT Status No Yes Yes Yes ACK

0 1 0 OUT N/Status No Yes Yes Yes STALL

0 1 0 OUT Error No Yes No No None

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Document #: 38-08026 Rev. *A Page 15 of 25

6.9.2.2 Endpoint 0 Transmit

The USB Endpoint 0 TX Register located at I/O address 0x10

controls data transmission from Endpoint 0 (see Figure 6-22).

This is a read/write register. All bits are cleared during reset.

Bits 0 to 3 indicate the numbers of data bytes to be transmitted

during an IN packet, valid values are 0 to 8 inclusive. Bit 4

indicates that a received DATA packet error (CRC, PID, or

bitstuffing error) occurred during a SETUP or OUT data phase.

Setting the Stall bit (bit 5) stalls IN and OUT packets. This bit

is cleared whenever a SETUP packet is received by

Endpoint 0. Bit 6 (Data 1/0) must be set to 0 or 1 to select the

DATA packet’s toggle state (0 for DATA0, 1 for DATA1).

After the transmit data has been loaded into the FIFO, bit 6

should be set according to the data toggle state and bit 7 set

to “1”. This enables the USB Controller to respond to an IN

packet. Bit 7 is cleared and an Endpoint 0 interrupt is

generated by the SIE once the host acknowledges the data

transmission. Bit 7 is also cleared when a SETUP token is

received. The Interrupt Service Routine can check bit 7 to

confirm that the data transfer was successful.

6.9.3 Endpoint 1

Endpoint 1 is capable of transmit only. The data to be trans-

mitted is stored in the 8-byte Endpoint 1 FIFO located at data

memory space 0x78 to 0x7F.

6.9.3.1 Endpoint 1 Transmit

Transmission is controlled by the USB Endpoint 1 TX Register

located at I/O address 0x11 (see Figure 6-23). This is a

read/write register. All bits are cleared during reset.

Bits 0 to 3 indicate the numbers of data bytes to be transmitted

during an IN packet, valid values are 0 to 8 inclusive.

Bit 4 must be set before Endpoint 1 can be used. If this bit is

cleared, the USB Controller ignores all traffic to Endpoint 1.

Setting the Stall bit (bit 5) stalls IN and OUT packets until this

bit is cleared.

Bit 6 (Data 1/0) must be set to either 0 or 1 depending on the

data packet’s toggle state, 0 for DATA0, 1 for DATA1.

After the transmit data has been loaded into the FIFO, bit 6

should be set according to the data toggle state and bit 7 set

to “1”. This enables the USB Controller to respond to an IN

packet. Bit 7 is cleared and an Endpoint 1 interrupt is

generated by the SIE once the host acknowledges the data

transmission.

6.9.4 USB Status and Control

USB status and control is regulated by USB Status and Control

This is a read/write register. All reserved bits must be written

to zero. All bits in the register are cleared during reset.

Bit 0 is set by the SIE if any USB activity except idle (D+ LOW,

D– HIGH) is detected. The user program should check and

clear this bit periodically to detect any loss of bus activity.

Writing a 0 to this bit clears it. Writing a 1 does not change its

value.

Bit 1 is used to force the on-chip USB transmitter to the K state

which sends a Resume signal to the host. Bit 2 is used to force

the transmitter to the J state. This bit should normally be set to

zero. However, for resume signaling, force a J state for one

instruction before forcing resume.

Bit 3 is used to automatically respond to the Status stage OUT

of a control read transfer on Endpoint 0. A valid Status stage

OUT contains a DATA1 packet with 0 bytes of data. If the Statu-

sOuts bit is set, the USB engine responds to a valid Status

stage OUT with an ACK, and any other OUT with a STALL.

b7 b6 b5 b4 b3 b2 b1 b0

INEN DATA1/0 STALL ERR COUNT3 COUNT2 COUNT1 COUNT0

R/W R/W R/W R/W R/W R/W R/W R/W

00000000

Figure 6-22. USB Endpoint 0 TX Configuration Register (Address 0x10)

b7 b6 b5 b4 b3 b2 b1 b0

INEN DATA1/0 STALL EP1EN COUNT3 COUNT2 COUNT1 COUNT0

R/W R/W R/W R/W R/W R/W R/W R/W

00000000

Figure 6-23. USB Endpoint 1 TX Configuration Register (Address 0x11)

b7 b6 b5 b4 b3 b2 b1 b0

Reserved Reserved Reserved ENOUTS STATOUTS FORCEJ FORCEK BUSACT

R/W R/W R/W R/W

00000000

Figure 6-24. USB Status and Control Register (USB SCR – Address 0x13)

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P25

CY7C63001A-SC

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Manufacturer:

Cypress Semiconductor

Description:

IC MCU 4K LS USB MCU 20-SOIC

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