CY7C63001
A
CY7C63101
A
Document #: 38-08026 Rev. *A Page 19 of 25
7.0 Absolute Maximum Ratings
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with Power Applied......–0°C to +70°C
Supply Voltage on V
CC
Relative to V
SS
......... –0.5V to +7.0V
DC Input Voltage................................... –0.5V to +V
CC
+0.5V
DC Voltage Applied to Outputs in
High-Z state ......................................... –0.5V to +V
CC
+0.5V
Max. Output Current into Port 1 Pins .......................... 60 mA
Max. Output Current into Non-Port 1 Pins.................. 10 mA
Power Dissipation..................................................... 300 mW
Static Discharge Voltage ..........................................> 2000V
Latch-up Current
[1]
................................................ > 200 mA
8.0 Electrical Characteristics f
OSC
= 6 MHz; Operating Temperature = 0 to 70°C, V
CC
= 4.0 to 5.25V
Parameter Description Conditions Min. Max. Unit
General
I
CC
V
CC
Operating Supply Current 25 mA
I
SB1
Supply Current—Suspend Mode Resonator off, D– > Voh min
[2]
20 µA
I
SB2
Supply Current—Start-up Mode 4 mA
V
PP
Programming Voltage (disabled) –0.4 0.4 V
t
start
Resonator Start-up Interval Ceramic resonator 256 µs
t
watch
Watchdog Timer Period 7.168 8.192 ms
Power On Reset
t
VCCS
V
CC
Slew Linear ramp on V
CC
pin to V
CC
[3, 4]
0.010 1000 ms
USB Interface
V
oh
Static Output High 15k ± 5% to Gnd
[5,6]
2.8 3.6 V
V
ol
Static Output Low See Notes 5 and 6 0.3 V
V
di
Differential Input Sensitivity |(D+)–(D–)|, and Figure 6-26 0.2 V
V
cm
Differential Input Common Mode Range Figure 6-26 0.8 2.5 V
V
se
Single Ended Receiver Threshold 0.8 2.0 V
C
in
Transceiver Input Capacitance D+ to Vss; D- to Vss 20 pF
I
lo
Data Line (D+, D–) Leakage 0 V <(D+, D–)<3.3 V, Hi-Z State –10 10 µA
R
pu1
External Bus Pull-up Resistance, D– pin 1.5 k± 5% to 3.3V supply 1.425 1.575 k
R
pu2
External Bus Pull-up Resistance, D– pin 7.5 k± 1% to Vcc
[7]
7.425 7.575 k
R
pd
External Bus Pull-down Resistance 15 k± 5% 14.25 15.75 k
General Purpose I/O Interface
R
up
Pull-up Resistance 8 24 k
I
sink0(0)
Port 0 Sink Current (0), lowest current Vout = 2.0V DC, Port 0 only
[5]
0.1 0.3 mA
I
sink0(F)
Port 0 Sink Current (F), highest current Vout = 2.0V DC, Port 0 only
[5]
0.5 1.5 mA
I
sink1(0)
Port 1 Sink Current (0), lowest current Vout = 2.0V DC, Port 1 only
[5]
1.6 4.8 mA
I
sink1(F)
Port 1 Sink Current (F), highest current Vout = 2.0V DC, Port 1 only
[5]
Vout = 0.4V DC, Port 1 only
[5]
8
5
24 mA
mA
I
range
Sink Current max./min. Vout = 2.0V DC, Port 0 or 1
[5, 8]
4.5 5.5
I
lin
Differential Nonlinearity Port 0 or Port 1
[11]
0.5 l
SB
T
ratio
Tracking Ratio Port1 to Port0 Vout = 2.0V
[12]
14.4 19.6
t
sink
Current Sink Response Time Full scale transition 0.8 µs
I
max
Port 1 Max Sink Current Summed over all Port 1 bits 60 mA
Notes:
1. All pins specified for >200 mA positive and negative injection, except P1.0 is specified for >50 mA negative injection.
2. Cext at V
CC
or Gnd, Port 0 and Port1 at V
CC
.
3. Part powers up in suspend mode, able to be reset by USB Bus Reset.
4. POR may re-occur whenever V
CC
drops to approximately 2.5V.
5. Level guaranteed for range of V
CC
= 4.35V to 5.25V.
6. With R
pu1
of 1.5 KW±5% on D– to 3.3V regulator.
7. Maximum matched capacitive loading allowed on D+ and D– (including USB cable and host/hub) is approximately 230 pF.
8. I
range
= I
sink(F)
/I
sink(0 )
for each port 0 or 1 output.
CY7C63001
A
CY7C63101
A
Document #: 38-08026 Rev. *A Page 20 of 25
Notes:
9. C
load
of 200 (75 ns) to 600 pF (300 ns).
10. Measured at crossover point of differential data signals.
11. Measured as largest step size vs. nominal according to measured full scale and zero programmed values
12. T
ratio
= I
sink1(n)
/I
sink0(n)
for the same n.
13. Low to High transition.
14. This parameter is guaranteed, but not tested.
15. With Ports configured in Hi-Z mode.
P
max
Port 1 & Cext Sink Mode Dissipation Per pin 25 mW
V
ith
Input Threshold Voltage All ports and Cext
[13]
45% 65% V
CC
V
H
Input Hysteresis Voltage Port 0 and Port 1
[14]
6% 12% V
CC
V
HCext
Input Hysteresis Voltage, Cext Cext Pin Only
[14]
12% 30% V
CC
Iin Input Leakage Current, GPIO Pins Port 0 and Port 1, Vout = 0 or V
CC
[15]
–1 1 µA
I
inCx
Input Leakage Current, Cext Pin V
Cext
= 0 or V
CC
50 nA
I
Cext
Sink Current, Cext Pin V
Cext
= V
CC
618mA
V
ol1
Output LOW Voltage, Cext Pin V
CC
= Min., I
ol
= 2 mA 0.4 V
V
ol2
Output LOW Voltage, Cext Pin V
CC
= Min., I
ol
= 5 mA 2.0 V
9.0 Switching Characteristics
Parameter Description Conditions Min. Max. Unit
Clock
t
CYC
Input Clock Cycle Time 166.67 166.67 ns
t
CH
Clock HIGH Time 0.45 t
CYC
ns
t
CL
Clock LOW Time 0.45 t
CYC
ns
USB Driver Characteristics
t
r
USB Data Transition Rise Time
See Notes 5, 6, and 9 75 300 ns
t
f
USB Data Transition Fall Time See Notes 5, 6, and 9 75 300 ns
t
rfm
Rise/Fall Time Matching t
r
/t
f
80 125 %
V
crs
Output Signal Crossover Voltage See Note 5 1.3 2.0 V
USB Data Timing
t
drate
Low Speed Data Rate Ave. Bit Rate (1.5 Mb/s ± 1.5%) 1.4775 1.5225 Mb/s
t
djr1
Receiver Data Jitter Tolerance To Next Transition, Figure 9-3
[10]
–75 75 ns
t
djr2
Receiver Data Jitter Tolerance For Paired Transitions, Figure 9-3
[10]
–45 45 ns
t
deop
Differential to EOP Transition Skew Figure 9-4
[10]
–40 100 ns
t
eopr
EOP Width at Receiver Accepts as EOP
[10]
670 ns
t
lst
Width of SE0 Interval During
Differential Transition
210 ns
t
eopt
Source EOP Width 1.25 1.50 µs
t
udj1
Differential Driver Jitter To next transition, Figure 9-5 –95 95 ns
t
udj2
Differential Driver Jitter To paired transition, Figure 9-5 –150 150 ns
8.0 Electrical Characteristics f
OSC
= 6 MHz; Operating Temperature = 0 to 70°C, V
CC
= 4.0 to 5.25V (continued)
Parameter Description Conditions Min. Max. Unit
CY7C63001
A
CY7C63101
A
Document #: 38-08026 Rev. *A Page 21 of 25
Figure 9-1. Clock Timing
Figure 9-2. USB Data Signal Timing and Voltage Levels
Figure 9-3. Receiver Jitter Tolerance
Figure 9-4. Differential to EOP Transition Skew and EOP Width
CLOCK
t
CYC
t
CL
t
CH
90%
10%
90%
10%
D
D+
t
r
t
f
V
crs
V
oh
V
ol
Differential
Data Lines
Paired
Transitions
N * T
PERIOD
+ T
JR2
T
PERIOD
Consecutive
Transitions
N * T
PERIOD
+ T
JR1
T
JR
T
JR1
T
JR2
T
PERIOD
Differential
Data Lines
Crossover
Point
Crossover
Point Extended
Source EOP Width: T
EOPT
Receiver EOP Width: T
EOPR1
, T
EOPR2
Diff. Data to
SE0 Skew
N * T
PERIOD
+ T
DEOP

CY7C63001A-SC

Mfr. #:
Manufacturer:
Cypress Semiconductor
Description:
IC MCU 4K LS USB MCU 20-SOIC
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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