CY7C63001A-SC Datasheet CY7C63001A-PC, CY7C63001A-PXC, CY7C63001A-SC | P7-P9

CY7C63001

CY7C63101

Document #: 38-08026 Rev. *A Page 7 of 25

6.3.2 Watchdog Reset (WDR)

The Watchdog Timer Reset (WDR) occurs when the Most

Significant Bit of the 4-bit Watchdog Timer Register transitions

from LOW to HIGH. Writing any value to the write-only

Watchdog Restart Register at 0x21 clears the timer (firmware

should periodically write to the Watchdog Restart Register in

the ‘main loop’ of firmware). The Watchdog timer is clocked by

a 1.024-ms clock from the free-running timer. If 8 clocks occur

between writes to the timer, a WDR occurs and bit 6 of the

Status and Control Register is set to record the event. A

Watchdog Timer Reset lasts for 8.192 ms, at which time the

microcontroller begins execution at ROM address 0x00. The

USB transmitter is disabled by a Watchdog Reset because the

USB Device Address Register is cleared (otherwise, the USB

Controller would respond to all address 0 transactions). The

transmitter remains disabled until the WDR bit (bit 6) in the

Status and Control Register is reset to 0 by firmware.

6.3.3 USB Bus Reset

The USB Controller recognizes a USB Reset when a Single

Ended Zero (SE0) condition persists for at least 8–16 µs (the

Reset may be recognized for an SE0 as short as 8 µs, but it is

always recognized for an SE0 longer than 16 µs). SE0 is the

condition in which both the D+ line and the D– line are LOW.

Bit 5 of the Status and Control Register is set to record this

event. If the USB reset happens while the device is

suspended, the suspend condition is cleared and the clock

oscillator is restarted. However, the microcontroller is not

released until the USB reset is removed.

6.4 Instant-on Feature (Suspend Mode)

The USB Controller can be placed in a low-power state by

setting the Suspend bit (bit 3) of the Status and Control

USB receiver, the GPIO interrupt logic, and the Cext interrupt

logic. The clock oscillator and the free-running and Watchdog

timers are shut down.

The suspend mode is terminated when one of the following

three conditions occur:

1. USB activity

2. A GPIO interrupt

3. Cext interrupt

The clock oscillator, GPIO, and timers restart immediately

upon exiting suspend mode. The USB engine and microcon-

troller return to a fully functional state no more than 256 µs

later. Before servicing any interrupt requests, the microcon-

troller executes the instruction following the I/O write that

placed the device into suspend mode.

Both the GPIO interrupt and the Cext interrupt allow the USB

Controller to wake-up periodically and poll potentiometers,

optics, and other system components while maintaining a very

low average power consumption. The Cext Interrupt is

preferred for lowest power consumption.

For Cext to generate an “Instant-on” interrupt, the pin must be

connected to ground with an external capacitor and connected

to V

with an external resistor. A “0” is written to the Cext

Then, a “1” is written to disable the open-drain output driver. A

Schmitt trigger input circuit monitors the input and generates

a wake-up interrupt when the input voltage rises above the

input threshold. By changing the values of the external resistor

and capacitor, the user can fine tune the charge rate of the R-

C timing circuit. The format of the Cext register is shown in

Figure 6-5. Reading the register returns the value of the Cext

pin. During a reset, the Cext pin is HIGH.

Last write to

Watchdog Timer

No write to WDT

goes HIGH

Execution begins at

Reset Vector 0x00

7.168 to

8.192 ms

Figure 6-4. Watchdog Reset

b7 b6 b5 b4 b3 b2 b1 b0

Reserved Reserved Reserved Reserved Reserved Reserved Reserved CEXT

R/W

00000001

Figure 6-5. The Cext Register (Address 0x22)

CY7C63001

CY7C63101

Document #: 38-08026 Rev. *A Page 8 of 25

6.5 On-Chip Timer

The USB Controller is equipped with a free-running timer

driven by a clock one-sixth the resonator frequency. Bits 0

through 7 of the counter are readable from the read-only Timer

cleared during a Power-On Reset and whenever Suspend

mode is entered. Figure 6-6 illustrates the format of this

With a 6 MHz resonator, the timer resolution is 1 µs.

The timer generates two interrupts: the 128-µs interrupt and

the 1.024-ms interrupt.

6.6 General Purpose I/O Ports

Interface with peripherals is conducted via as many as 16

GPIO signals. These signals are divided into two ports: Port 0

and Port 1. Port 0 contains eight lines (P0.0–P0.7) and Port 1

contains up to eight lines (P1.0–P1.7). The number of external

I/O pins depends on the package type. Both ports can be

accessed by the IORD, IOWR, and IOWX instructions. The

Port 0 data register is located at I/O address 0x00 while the

Port 1 data register is located at I/O address 0x01. The

contents of both registers are set HIGH during a reset. Refer

to Figures 6-8 and 6-9 for the formats of the data registers. In

addition to supporting general input/output functions, each I/O

line can trigger an interrupt to the microcontroller. Please refer

to the interrupt section for more details.

Figure 6-6. Timer Register (Address 0x23)

b7 b6 b5 b4 b3 b2 b1 b0

T.7 T.6 T. 5 T.4 T.3 T. 2 T.1 T.0

RRRRRRRR

00000000

Figure 6-7. Timer Block Diagram

Resonator Clock/6

1.024-ms interrupt

128-

s interrupt

To Timer Register

b7 b6 b5 b4 b3 b2 b1 b0

P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0

R/W R/W R/W R/W R/W R/W R/W R/W

1 1 1 1 1 1 1 1

Figure 6-8. Port 0 Data Register (Address 0x00)

b7 b6 b5 b4 b3 b2 b1 b0

P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0

R/W R/W R/W R/W R/W R/W R/W R/W

1 1 1 1 1 1 1 1

Figure 6-9. Port 1 Data Register (Address 0x01)

CY7C63001

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Document #: 38-08026 Rev. *A Page 9 of 25

Each GPIO line includes an internal R

resistor. This resistor

provides both the pull-up function and slew control. Two

factors govern the enabling and disabling of each resistor: the

state of its associated Port Pull-up register bit and the state of

the Data Register bit. NOTE: The control bits in the Port Pull-

up register are active LOW.

A GPIO line is HIGH when a “1” is written to the Data Register

and a “0” is written to the respective Port Pull-up register.

Writing a “0” to the port Data Register disables the port’s Pull-

up resistor and outputs a LOW on the GPIO line regardless of

the setting in the Port Pull-up Register. The output goes to a

high-Z state if the Data Register bit and the Port Pull-up

diagram of one I/O line. The Port Isink Register is used to

control the output current level and it is described later in this

section. NOTE: The Isink logic block is turned off during

suspend mode (please refer to the Instant-on Feature section

for more details). Therefore, to prevent higher I

currents

during USB suspend mode, firmware must set ALL Port 0 and

Port 1 Data Register bits (which are not externally driven to a

known state), including those that are not bonded out on a

particular package, to “1” and all Port 0 and Port 1 Pull-Up

the Suspend bit (bit 3 of the Status and Control Register).

Table 6-2 is the Output Control truth table.

To configure a GPIO pin as an input, a “1” should be written to

the Port Data Register bit associated with that pin to disable

the pull-down function of the Isink DAC (see Figure 6-

10).When the Port Data Register is read, the bit value is a “1”

if the voltage on the pin is greater than the Schmitt trigger

threshold, or “0” if it is below the threshold. In applications

where an internal pull-up is required, the R

pull-up resistor

can be engaged by writing a “0” to the appropriate bit in the

Port Pull-up Register.

Both Port 0 and Port 1 Pull-up Registers are write only (see

Figures 6-11 and 6-12). The Port 0 Pull-up Register is located

at I/O address 0x08 and Port 1 Pull-up Register is mapped to

address 0x09. The contents of the Port Pull-up Registers are

cleared during reset, allowing the outputs to be controlled by

the state of the Data Registers. The Port Pull-up Registers also

select the polarity of transition that generates a GPIO interrupt.

A “0” selects a HIGH to LOW transition while a “1” selects a

LOW to HIGH transition.

Figure 6-10. Block Diagram of an I/O Line

Table 6-2. Output Control Truth Table

Data Register Port Pull-up Register Output at I/O Pin Interrupt Polarity

0 0 Sink Current (‘0’) High to Low

0 1 Sink Current (‘0’) Low to High

1 0 Pull-up Resistor (‘1’) High to Low

1 1 Hi-Z Low to High

GPIO

Isink

DAC

Port Isink

Port Data

Port Pull-Up

Data Bus

Schmitt

Trigger

Suspend

Bit

Disable

b7 b6 b5 b4 b3 b2 b1 b0

PULL0.7 PULL0.6 PULL0.5 PULL0.4 PULL0.3 PULL0.2 PULL0.1 PULL0.0

WWWWWWWW

00000000

Figure 6-11. Port 0 Pull-up Register (Address 0x08)

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P25

CY7C63001A-SC

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Manufacturer:

Cypress Semiconductor

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IC MCU 4K LS USB MCU 20-SOIC

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