2
DATA OUT
SIGNAL
DETECT
DATA IN
QUANTIZER IC
LED DRIVER IC
PIN PHOTODIODE
PRE-AMPLIFIER
SUBASSEMBLY
LED OPTICAL
SUBASSEMBLY
DATA OUT
DATA IN
MT-RJ
RECEPTACLE
R
X
SUPPLY
T
X
SUPPLY
R
X
GROUND
T
X
GROUND
The HFBR-5903 is also useful for both ATM 100 Mb/s inter
faces and Fast Ethernet 100 Base-FX interfaces. The ATM
Forum User-Network Interface (UNI) Standard, Version
3.0, de nes the Physical Layer for 100 Mb/s Multimode
Fiber Interface for ATM in Section 2.3 to be the FDDI PMD
Standard. Likewise, the Fast Ethernet Alliance de nes the
Physical Layer for 100 Base-FX for Fast Ethernet to be the
FDDI PMD Standard.
ATM applications for physical layers other than 100 Mb/s
Multimode Fiber Interface are supported by Avago
Technologies. Products are available for both the single-
mode and the multi mode ber SONET OC-3c (STS-3c),
SDH (STM-1) ATM interfaces and the 155 Mb/s-194 logic
output and the Signal Detect function. The Data output
is di erential. The Signal Detect output is single-ended.
Both Data and Signal Detect outputs are PECL compat-
ible, ECL referenced (shifted) to a +3.3 V power supply.
The receiver outputs, Data Out and Data Out Bar, are
squelched at Signal Detect Deassert. That is, when the
light input power decreases to a typical -38 dBm or less,
the Signal Detect Deasserts, i.e. the Signal Detect output
goes to a PECL low state. This forces the receiver outputs,
Data Out and Data Out Bar to go to steady PECL levels
High and Low respectively.
Package
The overall package concept for the Avago Technologies
transceiver consists of the following basic elements; two
optical subassemblies, an electrical subassembly and the
housing as illustrated in Figure 1.
The package outline drawing and pin out are shown in
Figures 2 and 3. The details of this package outline and
pin out are compliant with the multi source de nition of
the 2 x 5 DIP. The low pro le of the Avago Technologies
transceiver design complies with the maximum height
allowed for the MT-RJ connector over the entire length of
the package.
The optical subassemblies utilize a high-volume assembly
process together with low-cost lens elements which result
in a cost-e ective building block.
The electrical subassembly con sists of a high volume
multilayer printed circuit board on which the IC and
various surface-mounted passive circuit elements are
attached.
The receiver section includes an internal shield for the elec-
trical and optical subassemblies to ensure high immunity
to external EMI elds.
The outer housing is electrically conductive. The MT-RJ
port is molded of lled nonconductive plastic to provide
mechanical strength and electrical isolation. The solder
posts of the Avago Technologies design are isolated from
the internal circuit of the transceiver.
The transceiver is attached to a printed circuit board with
the ten signal pins and the two solder posts which exit
the bottom of the housing. The two solder posts provide
the primary mechanical strength to withstand the loads
imposed on the trans ceiver by mating with the MT-RJ
connectored ber cables.
Figure 1. Block Diagram.
