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HFBR-0560

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
7
The Avago Technologies 1300 nm receivers will tolerate
the worst case input optical jitter allowed in Sections
8.2 Active Input Interface of the FDDI PMD and LCF-PMD
standards without violating the worst case output electri-
cal jitter allowed in Table E1 of Annex E.
The jitter speci cations stated in the following 1300 nm
transceiver speci cation tables are derived from the values
in Table E1 of Annex E. They represent the worst case jitter
contribution that the trans ceivers are allowed to make to
the overall system jitter without violating the Annex E al-
location example. In practice the typical contribution of
the Avago Technologies trans ceivers is well below these
maximum allowed amounts.
Recommended Handling Precautions
Avago Technologies recommends that normal static pre-
cautions be taken in the handling and assembly of these
transceivers to prevent damage which may be induced
by electrostatic discharge (ESD). The HFBR-5900 series of
transceivers meet MIL-STD-883C Method 3015.4 Class 2
products.
Care should be used to avoid shorting the receiver data or
signal detect outputs directly to ground without proper
current limiting impedance.
Solder and Wash Process Compatibility
The transceivers are delivered with protective process
plugs inserted into the MT-RJ connector receptacle. This
process plug protects the optical subassemblies during
wave solder and aqueous wash processing and acts as a
dust cover during shipping.
These transceivers are compat ible with either industry
standard wave or hand solder processes.
Shipping Container
The transceiver is packaged in a shipping container
designed to protect it from mechanical and ESD damage
during shipment or storage.
Figure 8. Alternative Termination Circuits
o
V
EE
R
X
o
V
CC
R
X
o
SD
o
RD-
o
RD+
Z = 50 :
130 :
V
CC
(+3.3 V)
10 nF
Z = 50 :
130 :
82 : 82 :
TERMINATE AT
TRANSCEIVER INPUTS
Z = 50 :
Z = 50 :
10 9 8 7
6
SD
LVPECL
V
CC
(+3.3 V)
TERMINATE AT DEVICE INPUTS
LVPECL
V
CC
(+3.3 V)
PHY DEVICE
TD+
TD-
RD+
RD-
Z = 50 :
1 2 3 4
5
TD-
o
TD+
o
N/C
o
V
EE
T
X
o
V
CC
T
X
o
1 µH
C2
1 µH
C1
C3
10 µF
V
CC
(+3.3 V)
TX
RX
Note: C1 = C2 = C3 = 10 nF or 100 nF
10 nF
130 :
82 :
V
CC
(+3.3
V)
130 :
82 :
V
CC
(+3.3
V)
82 :
130 :
10 nF
8
Board Layout - Decoupling Circuit, Ground Planes and
Termination Circuits
It is important to take care in the layout of your circuit
board to achieve optimum perform ance from these trans-
ceivers. Figure 7 provides a good example of a schematic
for a power supply decoupling circuit that works well with
these parts. It is further recommended that a continuous
ground plane be provided in the circuit board directly
under the transceiver to provide a low inductance ground
for signal return current. This recommen dation is in keeping
with good high frequency board layout practices. Figures
7 and 8 show two recommended termination schemes.
Board Layout - Hole Pattern
The Avago Technologies trans ceiver complies with the
circuit board “Common Transceiver Footprint” hole pattern
de ned in the original multisource announce ment which
de ned the 2 x 5 package style. This drawing is repro duced
in Figure 9 with the addition of ANSI Y14.5M compliant
dimensioning to be used as a guide in the mechani cal
layout of your circuit board.
Regulatory Compliance
These transceiver products are intended to enable
commercial system designers to develop equipment
that complies with the various international regula-
tions governing certi ca tion of Information Technol-
ogy Equipment. See the Regulatory Compliance Table
for details. Additional information is available from your
Avago Technologies sales representative.
Figure 9. Recommended Board Layout Hole Pattern
DIMENSIONS IN MILLIMETERS (INCHES)
NOTES:
1. THIS FIGURE DESCRIBES THE RECOMMENDED CIRCUIT BOARD LAYOUT FOR THE MT-RJ
TRANSCEIVER PLACED AT .550 SPACING.
2. THE HATCHED AREAS ARE KEEP-OUT AREAS RESERVED FOR HOUSING STANDOFFS. NO
METAL TRACES OR GROUND CONNECTION IN KEEP-OUT AREAS.
3. 10 PIN MODULE REQUIRES ONLY 16 PCB HOLES, INCLUDING 4 PACKAGE GROUNDING TAB
HOLES CONNECTED TO SIGNAL GROUND.
4. THE SOLDER POSTS SHOULD BE SOLDERED TO CHASSIS GROUND FOR MECHANICAL
INTEGRITY AND TO ENSURE FOOTPRINT COMPATIBILITY WITH OTHER SFF TRANSCEIVERS.
Spacing Of Front
Housing Leads Holes
Holes For
Housing
Leads
13.34
(0.525)
KEEP OUT AREA
FOR PORT PLUG
7.59
(0.299)
3
(0.118)
3
(0.118)
6
(0.236)
4.57
(0.18)
17.78
(0.7)
27
(1.063)
1.778
(0.07)
7.112
(0.28)
Ø 0.81 ±0.1
(0.032±0.004)
3.08
(0.121)
Ø
2.29
(0.09)
7.11
(0.28
)
9.59
(0.378
)
3.08
(0.121
)
Ø 1.4 ±0.1
(0.055±0.004)
Ø 1.4 ±0.1
(0.055±0.004)
Ø 1.4 ±0.1
(0.055±0.004)
10.16
(0.4)
13.97
(0.55)
MIN.
3.56
(0.14)
7
(0.276)
10.8
(0.425)
2
(0.079
)
9
Regulatory Compliance Table
Feature Test Method Performance
Electrostatic Discharge
(ESD) to the Electrical Pins
MIL-STD-883C
Method 3015.4
Meets Class 2 (2000 to 3999 Volts).
Withstand up to 2200 V applied between electrical pins.
Electrostatic Discharge
ESD) to the MT-RJ Receptacle
Variation of
IEC 801-2
Typically withstand at least 25 kV without damage when the
MT-RJ Connector Receptacle is contacted by a Human Body
Model probe.
Electromagnetic
Interference (EMI)
FCC Class B
CENELEC CEN55022
VCCI Class 2
Transceivers typically provide a 10 dB margin to the noted
standard limits when tested at a certi ed test range with the
transceiver mounted to a circuit card without a chassis enclosure.
Immunity Variation of IEC 801-3 Typically show no measurable e ect from a 10 V/m  eld swept
from 10 to 450 MHz applied to the transceiver when mounted to
a circuit card without a chassis enclosure.
Eye Safety IEC 825 Issue 1 1993:11
Class 1
CENELEC EN60825 Class 1
Compliant per Avago Technologies testing under single fault
conditions.
TUV Certi cation: LED Class 1
Figure 10. Recommended Panel Mounting
DIMENSIONS IN MILLIMETERS (INCHES)
10.8 ±0.1
(0.425±0.004)
13.97
(0.55)
MIN.
0.25 ±0.1
(0.01 ±0.004)
(TOP OF PCB
TO
BOTTOM OF
OPENING)
9.8 ±0.1
(0.386±0.004)
14.79
(0.589
)
1
(0.039
)
3.8
(0.15
)
Electrostatic Discharge (ESD)
There are two design cases in which immunity to ESD
damage is important.
The  rst case is during handling of the transceiver prior
to mount ing it on the circuit board. It is important to use
normal ESD handling precautions for ESD sensitive devices.
These pre cautions include using grounded wrist straps,
work benches, and  oor mats in ESD controlled areas.
The second case to consider is static discharges to the
exterior of the equipment chassis con taining the trans-
ceiver parts. To the extent that the MT-RJ connector is
exposed to the outside of the equipment chassis it may
be subject to whatever ESD system level test criteria that
the equipment is intended to meet.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16

HFBR-0560

Mfr. #:
Buy HFBR-0560
Manufacturer:
Broadcom / Avago
Description:
Fiber Optic Development Tools MT-RJ 125Mb/s Fast E Evaluation Kit
Lifecycle:
New from this manufacturer.
Delivery:
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