15
Notes:
1. This is the maximum voltage that can be applied across the Di eren-
tial Transmitter Data Inputs to prevent damage to the input ESD
protection circuit.
2. The outputs are terminated with 50 connected to V
CC
-2 V.
3. The power supply current needed to operate the transmitter is
provided to di erential ECL circuitry. This circuitry maintains a nearly
con stant current ow from the power supply. Constant current
operation helps to prevent unwanted electrical noise from being
generated and conducted or emitted to neighboring circuitry.
4. This value is measured with the outputs terminated into 50
connected to V
CC
- 2 V and an Input Optical Power level of -14 dBm
average.
5a. The power dissipation of the transmitter is calculated as the sum of
the products of supply voltage and current.
5b. The power dissipation of the receiver is calcu lated as the sum of
the products of supply voltage and currents, minus the sum of the
products of the output voltages and currents.
6. This value is measured with respect to V
CC
with the output
terminated into 50 connected to V
CC
- 2 V.
7. The output rise and fall times are measured between 20% and 80%
levels with the output connected to V
CC
-2 V through 50 .
8. Duty Cycle Distortion contributed by the receiver is measured
at the 50% threshold using an IDLE Line State, 125 MBd (62.5
MHz square-wave), input signal. The input optical power level is
-20 dBm average. See Appli cation Information - Transceiver Jitter
Section for further information.
9. Data Dependent Jitter contributed by the receiver is speci ed with
the FDDI DDJ test pattern described in the FDDI PMD Annex A.5.
The input optical power level is -20 dBm average. See Application
Informa tion - Transceiver Jitter Section for further information.
10. Random Jitter contributed by the receiver is speci ed with an IDLE
Line State, 125 MBd (62.5 MHz square-wave), input signal. The input
optical power level is at maxi mum “PIN Min. (W)”. See Applica tion
Information - Transceiver Jitter Section for further information.
11. These optical power values are measured with the following
conditions:
The Beginning of Life (BOL) to the End of Life (EOL) optical power
degradation is typically 1.5 dB per the industry convention for
long wavelength LEDs. The actual degradation observed in
Avago Technologies’ 1300 nm LED products is < 1 dB, as speci ed
in this data sheet.
Over the speci ed operating voltage and temperature ranges.
With HALT Line State, (12.5 MHz square-wave), input signal.
At the end of one meter of noted optical ber with cladding
modes removed.
The average power value can be converted to a peak power value
by adding 3 dB. Higher output optical power transmitters are
available on special request. Please consult with your local Avago
Technologies sales representative for further details.
12. The Extinction Ratio is a measure of the modulation depth of the
optical signal. The data “0” output optical power is compared to the
data “1” peak output optical power and expressed as a percentage.
With the transmitter driven by a HALT Line State (12.5 MHz square-
wave) signal, the average optical power is measured. The data “1”
peak power is then calculated by adding 3 dB to the measured
average optical power. The data “0” output optical power is found
by measuring the optical power when the transmitter is driven by a
logic “0” input. The extinc tion ratio is the ratio of the optical power at
the “0” level compared to the optical power at the “1” level expressed
as a percentage or in decibels.
13. The transmitter provides compliance with the need for Transmit_
Disable commands from the FDDI SMT layer by providing an Output
Optical Power level of < -45 dBm average in response to a logic “0”
input. This speci cation applies to either 62.5/125 μm or 50/125 μm
ber cables.
14. This parameter complies with the FDDI PMD requirements for the
trade-o s between center wavelength, spectral width, and rise/fall
times shown in Figure 11.
15. This parameter complies with the optical pulse envelope from the
FDDI PMD shown in Figure 12. The optical rise and fall times are
measured from 10% to 90% when the transmitter is driven by the
FDDI HALT Line State (12.5 MHz square-wave) input signal.
16. Duty Cycle Distortion contributed by the transmitter is measured at
a 50% threshold using an IDLE Line State, 125 MBd (62.5 MHz square-
wave), input signal. See Application Information - Transceiver Jitter
Performance Section of this data sheet for further details.
17. Data Dependent Jitter contributed by the transmitter is speci ed
with the FDDI test pattern described in FDDI PMD Annex A.5. See
Applica tion Information - Transceiver Jitter Performance Section of
this data sheet for further details.
18. Random Jitter contributed by the transmitter is speci ed with an
IDLE Line State, 125 MBd (62.5 MHz square-wave), input signal. See
Application Information - Transceiver Jitter Performance Section of
this data sheet for further details.
19. This speci cation is intended to indicate the performance of the
receiver section of the transceiver when Input Optical Power signal
characteristics are present per the following de nitions. The Input
Optical Power dynamic range from the minimum level (with a
window time-width) to the maximum level is the range over which
the receiver is guaranteed to provide output data with a Bit Error
Rate (BER) better than or equal to 2.5 x 10
-10
.
At the Beginning of Life (BOL)
Over the speci ed operating temperature and voltage ranges
Input symbol pattern is the FDDI test pattern de ned in FDDI
PMD Annex A.5 with 4B/5B NRZI encoded data that contains
a duty cycle base-line wander e ect of 50 kHz. This sequence
causes a near worst case condition for inter-symbol interference.
Receiver data window time-width is 2.13 ns or greater and
centered at mid-symbol. This worst case window time-width is
the minimum allowed eye-opening presented to the FDDI PHY
PM_Data indication input (PHY input) per the example in FDDI
PMD Annex E. This minimum window time-width of 2.13 ns
is based upon the worst case FDDI PMD Active Input Interface
optical conditions for peak-to-peak DCD (1.0 ns), DDJ (1.2 ns) and
RJ (0.76 ns) presented to the receiver.
To test a receiver with the worst case FDDI PMD Active Input jitter
condition requires exacting control over DCD, DDJ and RJ jitter
compo nents that is di cult to implement with production test
equipment. The receiver can be equivalently tested to the worst
case FDDI PMD input jitter conditions and meet the minimum
output data window time-width of 2.13 ns. This is accom plished by
using a nearly ideal input optical signal (no DCD, insigni cant DDJ
and RJ) and measuring for a wider window time-width of 4.6 ns.
This is possible due to the cumula tive e ect of jitter components
through their superposition (DCD and DDJ are directly additive and
RJ components are rms additive). Speci cally, when a nearly ideal
input optical test signal is used and the maximum receiver peak-to-
peak jitter contributions of DCD (0.4 ns), DDJ (1.0 ns), and RJ (2.14
ns) exist, the minimum window time-width becomes 8.0 ns -0.4
ns - 1.0 ns - 2.14 ns = 4.46 ns, or conservatively 4.6 ns. This wider
window time-width of 4.6 ns guarantees the FDDI PMD Annex E
minimum window time-width of 2.13 ns under worst case input
jitter conditions to the Avago Technologies receiver.
Transmitter operating with an IDLE Line State pattern, 125 MBd
(62.5 MHz square-wave), input signal to simulate any cross-talk
present between the trans mit ter and receiver sections of the
transceiver.
20. All conditions of Note 19 apply except that the measurement is
made at the center of the symbol with no window time-width.
21. This value is measured during the transition from low to high
levels of input optical power. At Signal Detect Deassert, the receiver
outputs Data Out and Data Out Bar go to steady PECL levels High
and Low respectively.
