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LT3050EDDB-3.3#TRPBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P26
LT3050 Series
13
3050fa
PIN FUNCTIONS
REF/BYP (Pin 1): Bypass/Soft-Start. Connecting a single
capacitor from this pin to GND bypasses the LT3050’s
reference noise and soft-starts the reference. A 10nF by-
pass capacitor typically reduces output voltage noise to
30V
RMS
in a 10Hz to 100kHz bandwidth. Soft-start time
is directly proportional to the REF/BYP capacitor value.
If the LT3050 is placed in shutdown, REF/BYP is actively
pulled low by an internal device to reset soft-start. If low
noise or soft-start performance is not required, this pin
must be left fl oating (unconnected). Do not drive this pin
with any active circuitry. Because the REF/BYP pin is the
reference input to the error amplifi er, stray capacitance at
this point should be minimized. Special attention should
be given to any stray capacitances that can couple external
signals onto the REF/BYP pin producing undesirable output
transients or ripple. A minimum REF/BYP capacitance of
100pF is recommended.
I
MIN
(Pin 2): Minimum Output Current Programming
Pin. This pin is the collector of a PNP current mirror that
outputs 1/200th of the power PNP load current. This pin
is also the input to the minimum output current fault com-
parator. Connecting a resistor between I
MIN
and GND sets
the minimum output current fault threshold. For detailed
information on how to set the I
MIN
pin resistor value,
please see the Operation section.
A small external decoupling capacitor (10nF minimum)
is required to improve I
MIN
PSRR. If minimum output
current programming is not required, the I
MIN
pin must
be left fl oating (unconnected).
FAULT (Pin 3): Fault Pin. This is an open collector logic
pin which asserts during current limit, thermal limit or
a minimum current fault condition. The maximum low
logic output level is defi ned for sinking 100A of current.
Off state logic may be as high as 45V without damaging
internal circuitry regardless of the V
IN
used.
SHDN (Pin 4): Shutdown. Pulling the SHDN pin low puts
the LT3050 into a low power state and turns the output
off. Drive the SHDN pin with either logic or an open collec-
tor/drain with a pull-up resistor. The resistor supplies the
pull-up current to the open collector/drain logic, normally
several microamperes, and the SHDN pin current, typi-
cally less than 2A. If unused, connect the SHDN pin to
IN. The LT3050 does not function if the SHDN pin is not
connected. The SHDN pin cannot be driven below GND
unless tied to the IN pin. If the SHDN pin is driven below
GND while IN is powered, the output may turn on. SHDN
pin logic cannot be referenced to a negative rail.
IN (Pin 5,6): Input. These pins supply power to the device.
The LT3050 requires a local IN bypass capacitor if it is
located more than six inches from the main input fi lter
capacitor. In general, battery output impedance rises
with frequency, so adding a bypass capacitor in battery
powered circuits is advisable. A minimum input of 1µF
generally suffi ces.
OUT (Pin 7,8): Output. These pins supply power to the
load. Stability requirements demand a minimum 2.2F
ceramic output capacitor to prevent oscillations. Large
load transient applications require larger output capaci-
tors to limit peak voltage transients. See the Applications
Information section for details on transient response and
reverse output characteristics. Permissible output voltage
range for the adjustable voltage version is 600mV to 44.5V.
The top of the resistor divider setting output voltage in
the fi xed 3.3V and 5V versions connects directly to OUT
on the IC.
ADJ (Pin 9): Adjust. This pin is the error amplifi er’s inverting
terminal. Its typical bias of 16nA current fl ows out of the
pin (see curve of ADJ Pin Bias Current vs. Temperature
in the Typical Performance Characteristics section). The
typical ADJ pin voltage is 600mV referenced to GND.
GND (PIN 10, Exposed Pad Pin 13): Ground. The exposed
pad of the DFN and MSOP packages is an electrical con-
nection to GND. To ensure proper electrical and thermal
performance, solder Pin 13 to the PCB ground and tie
directly to Pin 10. Connect the bottom of the output volt-
age setting resistor divider directly to GND (Pin 10) for
optimum load regulation performance.
I
MAX
(Pin 11): Precision Current Limit Programming
Pin. This pin is the collector of a current mirror PNP that
is 1/200
th
the size of the output power PNP. This pin is
also the input to the current limit amplifi er. Current limit
threshold is set by connecting a resistor between the I
MAX
pin and GND.
LT3050 Series
14
3050fa
For detailed information on how to set the I
MAX
pin resistor
value, please see the Operation section.
The I
MAX
pin requires a 10nF decoupling capacitor to
ground. If not used, tie I
MAX
to GND.
I
MON
(Pin 12): Output Current Monitor. This pin is the
collector of a PNP current mirror that outputs 1/100
th
PIN FUNCTIONS
of the power PNP current. When OUT = I
MON
, the pin
current exactly equals 1/100
th
that of the output current.
For detailed information on how to calculate the output
current from the I
MON
pin, please see the Operation section.
The I
MON
pin requires a small (22nF minimum) external
decoupling capacitor. If the I
MON
pin is not used, it must
be tied to GND.
BLOCK DIAGRAM
+
–
+
–
+
–
4
9
11
12
2
3
1
IN
5, 6
R1
R1
D1
Q3
QI
MIN
1/200
QI
MON
1/100
QI
MAX
1/200
QPOWER
1
I
MAX
I
MIN
FAULT
I
MON
QFAULT
U1
GND
10, 13
REF/BYP
SHDN
ADJ
30k
R4
OUT
IDEAL
DIODE
D3
Q2
D2
ERROR
AMPLIFIER
THERMAL/
CURRENT LIMITS
CURRENT
LIMIT
AMPLIFIER
100k
R3
I
MIN
COMPARATOR
100k
R2
600mV
REFERENCE
3050 BD01
OUT
7, 8
+
–
R2
FIXED V
OUT
R1 R2
3.3V 60k 270k
5V 60k 440k
LT3050 Series
15
3050fa
OPERATION
I
MON
Pin Operation (Current Monitor)
The I
MON
pin is the collector of a PNP which mirrors the
LT3050 output PNP at a ratio of 1:100 (see block diagram
on page 11). The current sourced by the I
MON
pin is
~1/100
th
of the current sourced by the OUT pin when the
I
MON
and OUT pin voltages are equal and the device is not
operating in dropout. If the I
MON
and OUT pin voltages
are not the same, the ratio deviates from 1/100 due to
the Early voltages of the I
MON
and OUT PNPs according
to the equation:
I
IMON
I
OUT
1
I
MONR
v
70 V
IN
V
IMON
70 V
IN
V
OUT
¥
§
¦
´
µ
Early Voltage Compensation
124443444
where the Early voltage of the PNPs is 70V and I
MONR
is
a variable which represents the I
OUT
to I
MON
current ratio.
I
MONR
varies with V
IN
to V
OUT
voltage according to the
empirically derived equation:
I
MONR
= 97 + 5 • log
10
(1+V
IN
– V
OUT
) for (V
IN
– V
OUT
)
≥0.5
I
MONR
= 96 + 2 • (V
IN
– V
OUT
)
for (V
IN
– V
OUT
) < 0.5
The I
MON
pin current can be converted into a voltage for
use by monitoring circuitry simply by connecting the I
MON
pin to a resistor.
Connecting a resistor from I
MON
to GND converts the
I
MON
pin current into a voltage that can be monitored by
circuitry such as an ADC.
For example, a 1.2k resistor results in a I
MON
pin voltage
of 1.2V for an output current of 100mA and an output
voltage of 1.2V.
The output current of the device can be calculated from
the I
MON
pin voltage by the following equation:
I
OUT
I
MONR
I
OUT
I
MON
Ratio
{
v
V
IMON
R
IMON
I
IMON
123
v
70 V
IN
V
OUT
70 V
IN
V
IMON
¥
§
¦
´
µ
Early VoltageCompensation
124443444
A small decoupling capacitor (22nF minimum) from I
MON
to GND is required to improve I
MON
pin power supply
rejection. If the current monitor is not needed, it must be
tied to GND.
Open Circuit Detection (I
MIN
Pin)
The I
MIN
pin is the collector of a PNP which mirrors the
LT3050 output at a ratio of approximately 1:200 (see block
diagram on page 11). The I
MIN
fault comparator asserts
the FAULT pin if the I
MIN
pin voltage is below 0.6V. This
low output current fault threshold voltage (I
OPEN
) is set
by attaching a resistor from I
MIN
to GND.
R
IV
I
IMIN
OPEN OUT
OPEN
=
119 85 1 68 36 8.–(.–.• )•
This equation is empirically derived and partially
compensates for early voltage effects in the I
MIN
current
mirror. It is valid for an input voltage range from 0.6V
above the output to 10V above the output. It is valid for
output voltages up to 12V. The accuracy of this equation
for setting the resistor value is approximately ±2%. Unit
values are Amps, Volts, and Ohms.
If the open circuit detection function is not needed, the I
MIN
pin must be left fl oating (unconnected). A small decoupling
capacitor (10nF minimum) from I
MIN
to GND is required
to improve I
MIN
pin power supply rejection and to prevent
FAULT pin glitches.
See the Typical Performance Characteristics section for
additional information.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P26

LT3050EDDB-3.3#TRPBF

Mfr. #:
Buy LT3050EDDB-3.3#TRPBF
Manufacturer:
Analog Devices / Linear Technology
Description:
LDO Voltage Regulators 100mA, Low Noise Linear Regulator with Precision Current Limit and Diagnostic Functions
Lifecycle:
New from this manufacturer.
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