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ISL6622IBZ-T

P1-P3P4-P6P7-P9P10-P12
10
FN6470.2
October 30, 2008
components such as lead inductances and PCB
capacitances are also not taken into account. Figure 8
provides a visual reference for this phenomenon and its
potential solution.
Gate Drive Voltage Options
Intersil provides various gate drive voltage options in the
ISL6622 product family, as shown in Table 2.
The ISL6622 can drop the low-side MOSFET’s gate drive
voltage when operating in DEM, while the high-side FET’s
gate drive voltage of the DFN package can be connected to
VCC or LVCC.
The ISL6622A allows the low-side MOSFET(s) to operate
from an externally-provided rail as low as 5V, eliminating the
LDO losses, while the high-side MOSFET’s gate drive
voltage of the DFN package can be connected to VCC or
LVCC.
The ISL6622B sets the low-side MOSFET’s gate drive
voltage at a fixed, programmable LDO level, while the
high-side FETs’ gate drive voltage of the DFN package can
be connected to VCC or LVCC.
FIGURE 8. GATE TO SOURCE RESISTOR TO REDUCE
UPPER MOSFET MILLER COUPLING
VIN
Q
UPPER
D
S
G
R
G
R
UGPH
BOOT
C
DS
C
GS
C
GD
PHASE
UVCC
ISL6622
C
BOOT
UGATE
>
20kΩ
TABLE 2. ISL6622 FAMILY BIAS OPTIONS
POWER RAILS
LVCC
UVCC VCCPSI
= LOW PSI = HIGH
ISL6622 SOIC 5.75V 11.2V VCC Operating Voltage Ranges
from 6.8V to 13.2V
DFN Programmable 11.2V Own Rail
ISL6622A SOIC Own Rail VCC
DFN Own Rail Own Rail
ISL6622B SOIC 5.75V VCC
DFN Programmable Own Rail
ISL6622
11
FN6470.2
October 30, 2008
ISL6622
Dual Flat No-Lead Plastic Package (DFN)
D
E
A
B
0.10 MC
e
0.415
C
SECTION "C-C"
NX (b)
(A1)
2X
C
0.15
0.15
2X
B
NX L
REF.
(Nd-1)Xe
5
A
C
(DATUM B)
D2
D2/2
E2
E2/2
TOP VIEW
7
BOTTOM VIEW
5
6
INDEX
AREA
8
AB
NX
k
6
INDEX
AREA
(DATUM A)
12
N-1N
NX b
8
NX b
NX L
0.200
C
A
SEATING
PLANE
0.08
C
A3
SIDE VIEW
0.10 C
L10.3x3
10 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE
SYMBOL
MILLIMETERS
NOTESMIN NOMINAL MAX
A 0.80 0.90 1.00 -
A1 - - 0.05 -
A3 0.20 REF -
b 0.18 0.23 0.28 5,8
D 3.00 BSC -
D2 1.95 2.00 2.05 7,8
E 3.00 BSC -
E2 1.55 1.60 1.65 7,8
e 0.50 BSC -
k0.25 - - -
L0.300.35 0.40 8
N102
Nd 5 3
Rev. 3 6/04
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd refers to the number of terminals on D.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensions are provided to assist with PCB Land
Pattern Design efforts, see Intersil Technical Brief TB389.
FOR ODD TERMINAL/SIDE
C
L
e
TERMINAL TIP
L
CC
12
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6470.2
October 30, 2008
ISL6622
Small Outline Plastic Packages (SOIC)
INDEX
AREA
E
D
N
123
-B-
0.25(0.010) C AM BS
e
-A-
L
B
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
h x 45°
C
H
0.25(0.010) BM M
α
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
M8.15 (JEDEC MS-012-AA ISSUE C)
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A 0.0532 0.0688 1.35 1.75 -
A1 0.0040 0.0098 0.10 0.25 -
B 0.013 0.020 0.33 0.51 9
C 0.0075 0.0098 0.19 0.25 -
D 0.1890 0.1968 4.80 5.00 3
E 0.1497 0.1574 3.80 4.00 4
e 0.050 BSC 1.27 BSC -
H 0.2284 0.2440 5.80 6.20 -
h 0.0099 0.0196 0.25 0.50 5
L 0.016 0.050 0.40 1.27 6
N8 87
α
0° 8° 0° 8° -
Rev. 1 6/05
P1-P3P4-P6P7-P9P10-P12

ISL6622IBZ-T

Mfr. #:
Buy ISL6622IBZ-T
Manufacturer:
Renesas / Intersil
Description:
Gate Drivers SYNCH BUCK MSFT HV DRVR VR11 1 IND 8LD
Lifecycle:
New from this manufacturer.
Delivery:
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