ISL6622IBZ-T Datasheet ISL6622CBZ-T, ISL6622CRZ-T, ISL6622IRZ | P7-P9

FN6470.2

October 30, 2008

Gate Voltage Optimization Technology (GVOT)

The ISL6622 provides the user flexibility in choosing the

gate drive voltage for efficiency optimization. During light

load operation, the switching losses dominate system

performance. Dropping down to a lower drive voltage with

GVOT during light load operation can reduce the switching

losses and maximize system efficiency.

Figure 2 shows that the gate drive voltage optimization is

accomplished via an internal low drop out regulator (LDO)

that regulates the lower gate drive voltage. LVCC is driven to

a lower voltage depending on the state of the internal PSI

signal and the GD_SEL pin impedance. The input and

output of this internal regulator is the VCC and LVCC pins,

respectively. Both VCC and LVCC should be decoupled with

a high quality low ESR ceramic capacitor.

In the 8 Ld SOIC package, the ISL6622 drives the upper and

lower gates close to VCC during normal PWM mode, while

the lower gate drops down to a fixed 5.75V during PSI

mode.

The 10 Ld DFN part offers more flexibility: the upper gate can

be driven from 5V to 12V via the UVCC pin, while the lower

gate has a resistor-selectable drive voltage of 5.75V, 6.75V,

and 7.75V during PSI

mode. This provides the flexibility

necessary to optimize applications involving trade-offs

between gate charge and conduction losses. Table 1 shows

the LDO output (LVCC) level set by the PWM input and

GD_SEL pin impedance.

Figure 3 illustrates the internal LDO’s variation with the

average load current plotted over a range of temperatures

spanning from -40

°C to +120°C. Should finer tweaking of this

LVCC voltage be necessary, a resistor (R

) can be used to

shunt the LDO, as shown in Figure 2. The resistor delivers

part of the LGATE drive current, leaving less current going

through the internal LDO, elevating the LDO’s output

voltage. Further reduction in RCC’s value can raise the

LVCC voltage further, as desired.

Figure 4 also details the typical LDO performance when the

pass element is fully enhanced, as it is the case when the

driver operates in CCM.

Power-On Reset (POR) Function

During initial start-up, the VCC voltage rise is monitored.

Once the rising VCC voltage exceeds rising POR threshold,

operation of the driver is enabled and the PWM input signal

takes control of the gate drives. If VCC drops below the POR

falling threshold, operation of the driver is disabled.

TABLE 1. LDO OPERATION AND OPTIONS

PWM INPUT GD_SEL PIN LVCC @ 50mA DC LOAD

Floating 5.75V (Typical; Fixed in

SOIC Package)

4.5kΩ to GND 6.75V (Typical)

GND 7.75V (Typical)

DON’T CARE 11.20V (Typical)

FIGURE 2. GATE VOLTAGE OPTIMIZATION (GVOT) DETAIL

EXTERNAL CIRCUIT

ISL6622 INTERNAL CIRCUIT

VIN

VCC

LVCC

1µF

SET BY

PSI

AND

GD_SEL

GVOT

LDO

RCC = OPTION FOR HIGHER LVCC

RCC

THAN PRE-SET BY GD_SEL

LGATE

DRIVER

2.5V

FIGURE 3. TYPICAL LVCC VARIATION WITH LOAD (CCM)

10.6

10.8

11.0

11.2

11.4

11.6

11.8

12.0

0 20 40 60 80 100

AVERAGE LOAD CURRENT (mA)

VCC = 12V

LVCC VOLTAGE (V)

+40°C

FIGURE 4. TYPICAL LVCC VARIATION WITH LOAD (DEM)

5.0

5.5

6.0

6.5

7.0

7.5

8.0

8.5

9.0

0406080100

AVERAGE LOAD CURRENT (mA)

LVCC VOLTAGE (V)

GD_SEL TIED TO GND

GD_SEL 4.5kΩ TO GND

GD_SEL FLOATING

+40°C

+120°C

-40°C

+120°C

-40°C

+40°C

-40°C

+120°C

+40°C

ISL6622

FN6470.2

October 30, 2008

Pre-POR Overvoltage Protection

While VCC is below its POR level, the upper gate is held low

and LGATE is connected to the PHASE pin via an internal

10kΩ (typically) resistor. By connecting the PHASE node to

the gate of the low side MOSFET, the driver offers some

passive protection to the load if the upper MOSFET(s) is or

becomes shorted. If the PHASE node goes higher than the

gate threshold of the lower MOSFET, it results in the

progressive turn-on of the device and the effective clamping

of the PHASE node’s rise. The actual PHASE node clamping

level depends on the lower MOSFET’s electrical

characteristics, as well as the characteristics of the input

supply and the path connecting it to the respective PHASE

node.

Internal Bootstrap Device

The ISL6622 features an internal bootstrap Schottky diode.

Simply adding an external capacitor across the BOOT and

PHASE pins completes the bootstrap circuit. The bootstrap

function is also designed to prevent the bootstrap capacitor

from overcharging due to the large negative swing at the

trailing-edge of the PHASE node. This reduces the voltage

stress on the BOOT to PHASE pins.

The bootstrap capacitor must have a maximum voltage

rating well above the maximum voltage intended for UVCC.

Its minimum capacitance value can be estimated from

Equation 1:

where Q

is the amount of gate charge per upper MOSFET

at V

GS1

gate-source voltage and N

is the number of

control MOSFETs. The ΔV

BOOT_CAP

term is defined as the

allowable droop in the rail of the upper gate drive. Select

results are exemplified in Figure 5.

Power Dissipation

Package power dissipation is mainly a function of the

switching frequency (F

), the output drive impedance, the

layout resistance, and the selected MOSFET’s internal gate

resistance and total gate charge (Q

). Calculating the power

dissipation in the driver for a desired application is critical to

ensure safe operation. Exceeding the maximum allowable

power dissipation level may push the IC beyond the maximum

recommended operating junction temperature. The DFN

package is more suitable for high frequency applications. See

“Layout Considerations” on page 9 for thermal impedance

improvement suggestions. The total gate drive power losses

due to the gate charge of MOSFETs and the driver’s internal

circuitry and their corresponding average driver current can

be estimated using Equations 2 and 3, respectively:

where the gate charge (Q

and Q

) is defined at a

particular gate to source voltage (V

GS1

and V

GS2

) in the

corresponding MOSFET datasheet; I

is the driver’s total

quiescent current with no load at both drive outputs; N

and N

are number of upper and lower MOSFETs,

respectively; UVCC and LVCC are the drive voltages for

both upper and lower FETs, respectively. The I

VCC

product is the quiescent power of the driver without a load.

BOOT_CAP

UGATE

ΔV

BOOT_CAP

--------------------------------------

≥

UGATE

UVCC•

GS1

------------------------------------

•=

(EQ. 1)

50nC

20nC

FIGURE 5. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE

VOLTAGE

ΔV

BOOT_CAP

(V)

BOOT_CAP

(µF)

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

0.30.0 0.1 0.2 0.4 0.5 0.6 0.90.7 0.8 1.0

UGATE

= 100nC

Qg_TOT

Qg_Q1

Qg_Q2

VCC•++=

(EQ. 2)

Qg_Q1

UVCC

•

GS1

---------------------------------------

• N

•=

Qg_Q2

LVCC

•

GS2

--------------------------------------

• N

•=

UVCC N

••

GS1

------------------------------------------------------

LVCC N

••

GS2

-----------------------------------------------------

⎝⎠

⎜⎟

⎛⎞

+•=

(EQ. 3)

ISL6622

FN6470.2

October 30, 2008

The total gate drive power losses are dissipated among the

resistive components along the transition path, as outlined in

Equation 4. The drive resistance dissipates a portion of the

total gate drive power losses, the rest will be dissipated by the

external gate resistors (R

and R

) and the internal gate

resistors (R

GI1

and R

GI2

) of MOSFETs. Figures 6 and 7 show

the typical upper and lower gate drives turn-on current paths.

Application Information

Layout Considerations

During switching of the devices, the parasitic inductances of

the PCB and the power devices’ packaging (both upper and

lower MOSFETs) leads to ringing, possibly in excess of the

absolute maximum rating of the devices. Careful layout can

help minimize such unwanted stress. The following advice is

meant to lead to an optimized layout:

• Keep decoupling loops (LVCC-GND and BOOT-PHASE)

as short as possible.

• Minimize trace inductance, especially low-impedance

lines: all power traces (UGATE, PHASE, LGATE, GND,

LVCC) should be short and wide, as much as possible.

• Minimize the inductance of the PHASE node: ideally, the

source of the upper and the drain of the lower MOSFET

should be as close as thermally allowable.

• Minimize the input current loop: connect the source of the

lower MOSFET to ground as close to the transistor pin as

feasible; input capacitors (especially ceramic decoupling)

should be placed as close to the drain of upper and source

of lower MOSFETs as possible.

In addition, for improved heat dissipation, place copper

underneath the IC whether it has an exposed pad or not. The

copper area can be extended beyond the bottom area of the

IC and/or connected to buried power ground plane(s) with

thermal vias. This combination of vias for vertical heat

escape, extended surface copper islands, and buried planes

combine to allow the IC and the power switches to achieve

their full thermal potential.

Upper MOSFET Self Turn-On Effect at Start-up

Should the driver have insufficient bias voltage applied, its

outputs are floating. If the input bus is energized at a high

dV/dt rate while the driver outputs are floating, due to

self-coupling via the internal C

of the MOSFET, the gate

of the upper MOSFET could momentarily rise up to a level

greater than the threshold voltage of the device, potentially

turning on the upper switch. Therefore, if such a situation

could conceivably be encountered, it is a common practice

to place a resistor (R

UGPH

) across the gate and source of

the upper MOSFET to suppress the Miller coupling effect.

The value of the resistor depends mainly on the input

voltage’s rate of rise, the C

ratio, as well as the gate-

source threshold of the upper MOSFET. A higher dV/dt, a

lower C

ratio, and a lower gate-source threshold

upper FET will require a smaller resistor to diminish the

effect of the internal capacitive coupling. For most

applications, the integrated 20kΩ resistor is sufficient, not

affecting normal performance and efficiency.

The coupling effect can be roughly estimated with

Equation 5, which assumes a fixed linear input ramp and

neglects the clamping effect of the body diode of the upper

drive and the bootstrap capacitor. Other parasitic

FIGURE 6. TYPICAL UPPER-GATE DRIVE TURN-ON PATH

FIGURE 7. TYPICAL LOWER-GATE DRIVE TURN-ON PATH

DR_UP

DR_LOW

VCC•++=

(EQ. 4)

DR_UP

HI1

EXT1

--------------------------------------

LO1

EXT1

----------------------------------------

⎝⎠

⎜⎟

⎛⎞

Qg_Q1

---------------------

•=

DR_LOW

HI2

EXT2

--------------------------------------

LO2

EXT2

----------------------------------------

⎝⎠

⎜⎟

⎛⎞

Qg_Q2

---------------------

•=

EXT1

GI1

-------------

EXT2

GI2

-------------

BOOT

HI1

LO1

PHASE

UVCC

LVCC

HI2

LO2

GS_MILLER

-------

rss

V–

-------

RC⋅

iss

⋅

----------------------------------

–

⎝⎠

⎜⎟

⎛⎞

⋅⋅=

UGPH

rss

iss

(EQ. 5)

ISL6622

P1-P3 P4-P6 P7-P9 P10-P12

ISL6622IBZ-T

Mfr. #:

Buy ISL6622IBZ-T

Manufacturer:

Renesas / Intersil

Description:

Gate Drivers SYNCH BUCK MSFT HV DRVR VR11 1 IND 8LD

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New from this manufacturer.

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ISL6622IBZ-T

ISL6622IBZ-T

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