1
®
X9420
Low Noise/Low Power/SPI Bus
Single Digitally Controlled (XDCP™)
Potentiometer
FEATURES
Solid-State Potentiometer
SPI Serial Interface
Register Oriented Format
Direct read/write/transfer wiper positions
Store as many as four positions per
potentiometer
Power Supplies
—V
CC
= 2.7V to 5.5V
V+ = 2.7V to 5.5V
V– = -2.7V to -5.5V
Low Power CMOS
Standby current < 1µA
High Reliability
Endurance–100,000 data changes per bit per
register
Register data retention–100 years
8-bytes of Nonvolatile EEPROM Memory
•10kΩ or 2.5kΩ Resistor Arrays
Resolution: 64 Taps Each Pot
14 Ld TSSOP and 16 Ld SOIC Packages
Pb-Free Plus Anneal Available (RoHS Compliant)
DESCRIPTION
The X9420 integrates a single digitally controlled
potentiometers (XDCP) on a monolithic CMOS
integrated microcircuit.
The digitally controlled potentiometer is implemented
using 63 resistive elements in a series array. Between
each element are tap points connected to the wiper
terminal through switches. The position of the wiper on
the array is controlled by the user through the SPI bus
interface. The potentiometer has associated with it a
volatile Wiper Counter Register (WCR) and 4
nonvolatile Data Registers (DR0:DR3) that can be
directly written to and read by the user. The contents
of the WCR controls the position of the wiper on the
resistor array through the switches. Power-up recalls
the contents of DR0 to the WCR.
The XDCP can be used as a three-terminal
potentiometer or as a two-terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.
BLOCK DIAGRAM
R0 R1
R2 R3
Wiper
Counter
Register
(WCR)
Interface
and
Control
Circuitry
HOLD
CS
SI
A0
V
H
/R
H
V
L
/R
L
Data
8
V
W
/R
W
SCK
S0
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
| Intersil (and design) is a registered trademark of Intersil Americas Inc.
XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
Data Sheet FN8195.1April 26, 2006
N
O
T
R
E
C
O
M
M
E
N
D
E
D
F
O
R
N
E
W
D
E
S
I
G
N
S
P
O
S
S
I
B
L
E
S
U
B
S
T
I
T
U
T
E
P
R
O
D
U
C
T
I
S
L
2
2
4
1
6
,
I
S
L
2
2
4
1
9
,
I
S
L
9
5
3
1
1
,
I
S
L
9
5
7
1
1
2
FN8195.1
April 26, 2006
Ordering Information
PART NUMBER
PART
MARKING V
CC
LIMITS (V)
POTENTIOMETER
ORGANIZATION
(k)
TEMP. RANGE
(°C) PACKAGE
PKG.
DWG. #
X9420WS16* X9420WS 5 ±10% 10 0 to +70 16 Ld SOIC (300 mil) M16.3
X9420WS16Z* (Note) X9420WS Z 0 to +70 16 Ld SOIC (300 mil) (Pb-free) M16.3
X9420WS16I* X9420WS I -40 to +85 16 Ld SOIC (300 mil) M16.3
X9420WS16IZ* (Note) X9420WS ZI -40 to +85 16 Ld SOIC (300 mil) (Pb-free) M16.3
X9420WV14* X9420 W 0 to +70 14 Ld TSSOP (4.4mm) M14.173
X9420WV14Z* (Note) X9420 WZ 0 to +70 14 Ld TSSOP (4.4mm) (Pb-free) M14.173
X9420WV14I* X9420 WI -40 to +85 14 Ld TSSOP (4.4mm) M14.173
X9420WV14IZ* (Note) X9420 WZI -40 to +85 14 Ld TSSOP (4.4mm) (Pb-free) M14.173
X9420YS16* X9420YS 2.5 0 to +70 16 Ld SOIC (300 mil) M16.3
X9420YS16Z* (Note) X9420YS Z 0 to +70 16 Ld SOIC (300 mil) (Pb-free) M16.3
X9420YS16I* X9420YS I -40 to +85 16 Ld SOIC (300 mil) M16.3
X9420YS16IZ* (Note) X9420YS ZI -40 to +85 16 Ld SOIC (300 mil) (Pb-free) M16.3
X9420YV14* X9420 Y 0 to +70 14 Ld TSSOP (4.4mm) M14.173
X9420YV14Z* (Note) X9420 YZ 0 to +70 14 Ld TSSOP (4.4mm) (Pb-free) M14.173
X9420YV14I* X9420 YI -40 to +85 14 Ld TSSOP (4.4mm) M14.173
X9420YV14IZ* (Note) X9420 YZI -40 to +85 14 Ld TSSOP (4.4mm) (Pb-free) M14.173
X9420WS16-2.7* X9420WS F 2.7 to 5.5 10 0 to +70 16 Ld SOIC (300 mil) M16.3
X9420WS16Z-2.7* (Note) X9420WS ZF 0 to +70 16 Ld SOIC (300 mil) (Pb-free) M16.3
X9420WS16I-2.7* X9420WS G -40 to +85 16 Ld SOIC (300 mil) M16.3
X9420WS16IZ-2.7*
(Note)
X9420WS ZG -40 to +85 16 Ld SOIC (300 mil) (Pb-free) M16.3
X9420WV14-2.7* X9420 WF 0 to +70 14 Ld TSSOP (4.4mm) M14.173
X9420WV14Z-2.7* (Note) X9420 WZF 0 to +70 14 Ld TSSOP (4.4mm) (Pb-free) M14.173
X9420WV14I-2.7* X9420 WG -40 to +85 14 Ld TSSOP (4.4mm) M14.173
X9420WV14IZ-2.7*
(Note)
X9420 WZG -40 to +85 14 Ld TSSOP (4.4mm) (Pb-free) M14.173
X9420YS16-2.7* X9420YS F 2.7 to 5.5 2.5 0 to +70 16 Ld SOIC (300 mil) M16.3
X9420YS16Z-2.7* (Note) X9420YS ZF 0 to +70 16 Ld SOIC (300 mil) (Pb-free) M16.3
X9420YS16I-2.7* X9420YS G -40 to +85 16 Ld SOIC (300 mil) M16.3
X9420YS16IZ-2.7* (Note) X9420YS ZG -40 to +85 16 Ld SOIC (300 mil) (Pb-free) M16.3
X9420YV14-2.7* X9420 YF 0 to +70 14 Ld TSSOP (4.4mm) M14.173
X9420YV14Z-2.7* (Note) X9420 YZF 0 to +70 14 Ld TSSOP (4.4mm) (Pb-free) M14.173
X9420YV14I-2.7* X9420 YG -40 to +85 14 Ld TSSOP (4.4mm) M14.173
X9420YV14IZ-2.7* (Note) X9420 YZG -40 to +85 14 Ld TSSOP (4.4mm) (Pb-free) M14.173
*Add "T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
X9420
3
FN8195.1
April 26, 2006
PIN DESCRIPTIONS
Host Interface Pins
Serial Output (SO)
SO is a push/pull serial data output pin. During a read
cycle, data is shifted out on this pin. Data is clocked
out by the falling edge of the serial clock.
Serial Input
SI is the serial data input pin. All opcodes, byte
addresses and data to be written to the potentiometer
and pot register are input on this pin. Data is latched
by the rising edge of the serial clock.
Serial Clock (SCK)
The SCK input is used to clock data into and out of the
X9420.
Chip Select (CS
)
When CS
is HIGH, the X9420 is deselected and the
SO pin is at high impedance, and (unless an internal
write cycle is underway) the device will be in the
standby state. CS
LOW enables the X9420, placing it
in the active power mode. It should be noted that after
a power-up, a HIGH to LOW transition on CS
is
required prior to the start of any operation.
Hold (HOLD
)
HOLD
is used in conjunction with the CS pin to select
the device. Once the part is selected and a serial
sequence is underway, HOLD
may be used to pause
the serial communication with the controller without
resetting the serial sequence. To pause, HOLD
must
be brought LOW while SCK is LOW. To resume
communication, HOLD
is brought HIGH, again while
SCK is LOW. If the pause feature is not used, HOLD
should be held HIGH at all times.
Device Address (A
0
)
The address inputs is used to set the least significant
bit of the 8-bit slave address. A match in the slave
address serial data stream must be made with the
address input in order to initiate communication with
the X9420. A maximum of 2 devices may occupy the
SPI serial bus.
Potentiometer Pins
V
H
/R
H
, V
L
/R
L
The V
H
/R
H
and V
L
/R
L
input are equivalent to the
terminal connections on either end of a mechanical
potentiometer.
V
W
/R
W
The wiper output is equivalent to the wiper output of a
mechanical potentiometer.
Hardware Write Protect Input (WP
)
The WP
pin when LOW prevents nonvolatile writes to
the Data Registers. Writing to the Wiper Counter
Register is not restricted.
Analog Supplies (V+, V-)
The analog supplies V+, V- are the supply voltages for
the XDCP analog section.
System/Digital Supply (V
CC
)
V
CC
is the supply voltage for the system/digital
section. V
SS
is the system ground.
PIN CONFIGURATION
V
CC
CS
R
L
/V
L
SI
WP
V
SS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V+
NC
A0
SO
HOLD
SCK
NC
V-
DIP/SOIC
X9420
R
H
/V
H
R
W
/V
W
TSSOP
V
CC
CS
R
L
/V
L
SI
WP
V
SS
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V+
A0
SO
HOLD
SCK
V-
X9420
R
H
/V
H
R
W
/V
W
X9420

X9420YS16-2.7T1

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
IC XDCP SGL 64-TAP 2.5K 16-SOIC
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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