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X9420YS16-2.7T1

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19
16
FN8195.1
April 26, 2006
XDCP Timing (for All Load Instructions)
XDCP Timing (for Increment/Decrement Instruction)
Write Protect and Device Address Pins Timing
...
CS
SCK
SI
MSB LSB
V
W
t
WRL
...
SO
High Impedance
...
CS
SCK
SO
SI
ADDR
t
WRID
High Impedance
V
W
...
Inc/Dec
Inc/Dec
...
CS
WP
A0
A1
t
WPASU
t
WPAH
(Any Instruction)
X9420
17
FN8195.1
April 26, 2006
APPLICATIONS INFORMATION
Electronic potentiometers provide three powerful application advantages: (1) the variability and reliability of a solid-
state potentiometer, (2) the flexibility of computer-based digital controls, and (3) the retentivity of nonvolatile memory
used for the storage of multiple potentiometer settings or data.
Basic Configurations of Electronic Potentiometers
Basic Circuits
V
R
V
W
V
R
I
Three terminal Potentiometer;
Variable voltage divider
Two terminal Variable Resistor;
Variable current
V
H
V
L
Noninverting Amplifier
Voltage Regulator
Offset Voltage Adjustment Comparator with Hysterisis
+
–
V
S
V
O
R
2
R
1
V
O
= (1+R
2
/R
1
)V
S
R
1
R
2
I
adj
V
O
(REG) = 1.25V (1+R
2
/R
1
)+I
adj
R
2
V
O
(REG)V
IN
317
+
–
V
S
V
O
R
2
R
1
V
UL
= {R
1
/CR
1
+R
2
} V
O
(max)
V
LL
= {R
1
/CR
1
+R
2
} V
O
(min)
100kΩ
10kΩ10kΩ
10kΩ
-12V+12V
TL072
+
–
V
S
V
O
R
2
R
1
}
}
+5V
-5V
LM308A
Cascading TechniquesBuffered Reference Voltage
–
+
+5V
R
1
+V
-5V
V
W
V
W
V
OUT
= V
W
OP-07
V
W
V
W
+V
+V +V
X
(a) (b)
X9420
18
FN8195.1
April 26, 2006
X9420
Thin Shrink Small Outline Plastic Packages (TSSOP)
α
INDEX
AREA
E1
D
N
123
-B-
0.10(0.004) C AM BS
e
-A-
b
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
c
E
0.25(0.010) BM M
L
0.25
0.010
GAUGE
PLANE
A2
NOTES:
1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AC, Issue E.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable dambar
protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimen-
sion at maximum material condition. Minimum space between protru-
sion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact. (Angles in degrees)
0.05(0.002)
M14.173
14 LEAD THIN SHRINK SMALL OUTLINE PLASTIC
PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A - 0.047 - 1.20 -
A1 0.002 0.006 0.05 0.15 -
A2 0.031 0.041 0.80 1.05 -
b 0.0075 0.0118 0.19 0.30 9
c 0.0035 0.0079 0.09 0.20 -
D 0.195 0.199 4.95 5.05 3
E1 0.169 0.177 4.30 4.50 4
e 0.026 BSC 0.65 BSC -
E 0.246 0.256 6.25 6.50 -
L 0.0177 0.0295 0.45 0.75 6
N14 147
α
0
o
8
o
0
o
8
o
-
Rev. 2 4/06
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19

X9420YS16-2.7T1

Mfr. #:
Buy X9420YS16-2.7T1
Manufacturer:
Renesas / Intersil
Description:
IC XDCP SGL 64-TAP 2.5K 16-SOIC
Lifecycle:
New from this manufacturer.
Delivery:
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