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AD8012ARZ-REEL

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
REV. B–12–
AD8012
THEORY OF OPERATION
The AD8012 is a dual, high speed CF amplifier that attains new
levels of bandwidth (BW), power, distortion, and signal swing
capability. Its wide dynamic performance (including noise) is
the result of both a new complementary high speed bipolar
process and a new and unique architectural design. The AD8012
uses a two-gain stage complementary design approach versus
the traditional single-stage complementary mirror structure
sometimes referred to as the Nelson amplifier. Though twin
stages have been tried before, they typically consumed high
power since they were of a folded cascade design, similar to that
of the AD9617. This design allows for the standing or quiescent
current to add to the high signal or slew current-induced stages.
In the time domain, the large signal output rise/fall time and
slew rate is typically controlled by the small signal BW of the
amplifier and the input signal step amplitude, respectively, and
not the dc quiescent current of the gain stages (with the excep-
tion of input level shift diodes Q1/Q2). Using two stages versus
one also allows for a higher overall gain bandwidth product
(GBWP) for the same power, resulting in lower signal distortion
and the ability to drive heavier external loads. In addition, the
second-gain stage also isolates (divides down) A3’s input
reflected load drive and the nonlinearities created, resulting in
relatively lower distortion and higher open-loop gain.
Overall, when high external load drive and low ac distortion is a
requirement, a twin-gain stage integrating amplifier like the
AD8012 will provide excellent results for lower power over the
traditional single stage complementary devices. In addition,
because the AD8012 is a CF amplifier, closed-loop BW variations
versus external gain variations (varying RN) will be much lower
compared to a VF op amp, where the BW varies inversely with
gain. Another key attribute of this amplifier is its ability to run on
a single 5 V supply partially because of its wide common-mode
input and output voltage range capability. For 5 V supply
operation, the device consumes half the quiescent power (vs.
10 V supply) with little degradation in its ac and dc perfor-
mance characteristics. See data sheet comparisons.
DC GAIN CHARACTERISTICS
Gain stages A1/A1B and A2/A2B combined provide negative
feedforward transresistance gain as shown in Figure 4. Stage A3
is a unity-gain buffer that provides external load isolation to A2.
Each stage uses a symmetrical complementary design (A3 is also
complementary though not explicitly shown). This is done to
reduce both second-order signal distortion and overall quiescent
power as previously described. In the quasi dc to low frequency
region, the closed-loop gain relationship can be approximated as:
These basic relationships are common to all traditional opera-
tional amplifiers.
V
P
Q1
Q2
IPP
IPN
INP
IPN
V
N
A1
A1
Z
I
IQ1
Q3
Q4
IE
C
P
1
C
P
1
Z2
A2
C
L
R
N
ICQ – IO
R
F
V
O
C
D
ICQ + IO
IQ1
AD8012
A2
C
P
2
Z1 = R1 || C1
Z1
C
D
A3
R
L
Z1
–V
I
–V
I
IR – IFC
IR + IFC
+ Ð
V
O
I
Figure 4. Simplified Block Diagram
G= +R R
G=–R R
FN
FN
1/
/
noninverting operation
inverting operation
REV. B
AD8012
–13–
APPLICATIONS
Line Driving for HDSL
High bitrate digital subscriber line (HDSL) is becoming
popular as a means of providing full duplex data communication at
rates up to 1.544 MBPS or 2.048 MBPS over moderate distances
via conventional telephone twisted pair wires. Traditional T1
(E1 in Europe) requires repeaters every 3,000 feet to 6,000 feet
to boost the signal strength and allow transmission over distances
of up to 12,000 feet. In order to achieve repeaterless transmission
over this distance, an HDSL modem requires a transmitted
power level of 13.5 dBm (assuming a line impedance of 135 Ω).
HDSL uses the two binary/one quaternary line code (2B1Q).
A sample 2B1Q waveform is shown in Figure 5. The digital bit
stream is broken up into groups of two bits. Four analog volt-
ages (called quaternary symbols) are used to represent the four
possible combinations of two bits. These symbols are assigned
the arbitrary names +3, +1, –1, and –3. The corresponding
voltage levels are produced by a DAC that is usually part of an
analog front end circuit (AFEC). Before being applied to the
line, the DAC output is low-pass filtered and acquires the sinu-
soidal form shown in Figure 5. Finally, the filtered signal is
applied to the line driver. The line voltages that correspond to
the quaternary symbols +3, +1, –1, and –3 are 2.64 V, 0.88 V,
–0.88 V, and –2.64 V. This gives a peak-to-peak line voltage of
5.28 V.
VOLTAGE
+3 2.64V
+1 0.88V
–1 –0.88V
–3 –2.64V
SYMBOL
NAME
DAC
OUTPUT
FILTERED
OUTPUT
TO LINE
DRIVER
–1
01
+3
10
+1
11
–3
00
–3
00
+1
11
+3
10
–3
00
–1
01
–1
01
+1
11
–1
01
–3
00
Figure 5. Time Domain Representation of an HDSL Signal
Many of the elements of a classic differential line driver are
shown in the HDSL line driver in Figure 6. A 6 V peak-to-peak
differential signal is applied to the input. The differential gain of
the amplifier (1+2 R
F
/R
G
) is set to +2, so the resulting differen-
tial output signal is 12 V p-p.
As is normal in telephony applications, a transformer galvani-
cally isolates the differential amplifier from the line. In this case,
a 1:1 turns ratio is used. In order to correctly terminate the line,
it is necessary to set the output impedance of the amplifier to be
equal to the impedance of the line being driven (135 Ω in this
case). Because the transformer has a turns ratio of 1:1, the
impedance reflected from the line is equal to the line impedance
of 135 Ω (R
REFL
= R
LINE
/Turns Ratio
2
). As a result, two 66.5 Ω
resistors correctly terminate the line.
6V p-p
12V p-p
1:1
+5V
–5V
R
F
750
R
F
750
R
G
1.5k
1/2
AD8012
1/2
AD8012
0.1F
0.1F
66.5
66.5
6V p-p
1:1
135
TO
RECEIVER
CIRCUITRY
TO
RECEIVER
CIRCUITRY
GAIN = +2
UP TO
12,000 FEET
+
–
Figure 6. Differential for HDSL Applications
The immediate effect of back-termination is that the signal from
the amplifier is halved before being applied to the line. This
doubles the power the amplifier must deliver. However, the
back-termination resistors also play an important second role.
Full-duplex data transmission systems like HDSL simulta-
neously transmit data in both directions. As a result, the signal
on the line and across the back termination resistors is the
composite of the transmitted and received signal. The termina-
tion resistors are used to tap off this signal and feed it to the
receive circuitry. Because the receive circuitry “knows” what is
being transmitted, the transmitted data can be subtracted from
the digitized composite signal to reveal the received data.
Driving a line with a differential signal offers a number of
advantages compared to a single-ended drive. Because the two
outputs are always 180 degrees out of phase relative to one
another, the differential signal output is double the output
amplitude of either of the op amps. As a result, the differential
amplifier can have a peak-to-peak swing of 16 V (each op amp
can swing to ±4 V), even though the power supply is ±5 V.
In addition, even-order harmonics (second, fourth, sixth, and
so on.) of the two single-ended outputs tend to cancel out one
another, so the total harmonic distortion (quadratic sum of all
harmonics) decreases compared to the single-ended case, even
as the signal amplitude is doubled. This is particularly advan-
tageous in the case of the second harmonic. Because it is very
close to the fundamental, filtering becomes difficult. In this
application, the THD is dominated by the third harmonic,
which is 65 dB below the carrier (i.e., spurious-free dynamic
range = –65 dBc).
Differential line driving also helps to preserve the integrity of the
transmitted signal in the presence of electromagnetic interfer-
ence (EMI). EMI tends to induce itself equally onto both the
positive and negative signal lines. As a result, a receiver with
good common-mode rejection will amplify the original signal
while rejecting induced (common-mode) EMI.
REV. B–14–
AD8012
Choosing the Appropriate Turns Ratio for the Transformer
Increasing the peak-to-peak output signal of the amplifier in the
previous example and adding a variation in the turns ratio of the
transformer can yield further enhancements to the circuit. The
output signal swing of the AD8012 can be increased to about
±3.9 V before clipping occurs. This increases the peak-to-peak
output of the differential amplifier to 15.6 V. Because the signal
applied to the primary winding is now bigger, the transformer
turns ratio of 1:1 can be replaced with a (step-down) turns ratio
of about 1.3:1 (from amplifier to line). This steps the 7.8 V
peak-to-peak primary voltage down to 6 V. This is the same
secondary voltage of the earlier examples, so the resulting power
delivered to the line is the same.
The received signal, which is small relative to the transmitted
signal, will, however, be stepped up by a factor of 1.3. Amplifying
the received signal in this manner enhances its signal-to-noise
ratio and is useful when the received signal is small compared to
the to-be-transmitted signal.
The impedance reflected from the 135 Ω line now becomes
228 Ω (1.3
2
⫻ 135 Ω). With a correctly terminated line, the
amplifier must now drive a total load of 456 Ω (114 Ω + 114 Ω
+ 228 Ω), considerably more than the original 270 Ω load. This
reduces the drive current from the op amps by about 40%.
More significant, however, is the reduction in dynamic power
consumption—that is, the power the amplifier must consume in
order to deliver the load power. Increasing the output signal so
that it is as close as possible to the power rails minimizes the
power consumed in the amplifier.
There is, however, a price to pay in terms of increased signal
distortion. Increasing the output signal of each op amp from the
original ± 3 V to ±3.9 V reduces the spurious-free dynamic
range (SFDR) from –65 dB to –50 dB (measured at 500 kHz),
even though the overall load impedance has increased from
270 Ω to 456 Ω.
LAYOUT CONSIDERATIONS
The specified high speed performance of the AD8012 requires
careful attention to board layout and component selection.
Table I shows recommended component values for the AD8012
and Figures 8–13 show recommended layouts for the 8-lead
SOIC and MSOP packages for a positive gain. Proper RF
design techniques and low parasitic component selections
are mandatory.
The PCB should have a ground plane covering all unused
portions of the component side of the board to provide a low
impedance ground path. The ground plane should be removed
from the area near the input pins to reduce stray capacitance.
Chip capacitors should be used for supply bypassing (see Figure 7).
One end should be connected to the ground plane and the other
within 1/8 inch of each power pin. An additional (4.7 µF to 10 µF)
tantalum electrolytic capacitor should be connected in parallel.
The feedback resistor should be located close to the inverting
input pin in order to keep the stray capacitance at this node to
a minimum. Capacitance greater than 1.5 pF at the inverting
input will significantly affect high speed performance when
operating at low noninverting gains.
Stripline design techniques should be used for long signal traces
(greater than about 1 inch). They should be designed with the
proper system characteristic impedance and be properly termi-
nated at each end.
0.1F
INVERTING CONFIGURATION
V
OUT
R
F
10F
NONINVERTING CONFIGURATION
V
OUT
R
G
R
F
R
T
0.1F
10F
R
T
V
IN
R
G
V
IN
*R
O
CHOSEN FOR CHARACTERISTIC IMPEDANCE.
+V
S
+
+
–V
S
R
O
*
R
O
*
*R
O
CHOSEN FOR CHARACTERISTIC IMPEDANCE.
Figure 7. Inverting and Noninverting Configurations
Table I. Typical Bandwidth vs. Gain Setting Resistors
Small Signal –3 dB BW (MHz),
Gain R
F
R
G
R
T
V
S
= 5 V, R
L
= 1 k
–1 750 Ω 750 Ω 53.6 Ω 110
+1 750 Ω 49.9 Ω 350
+2 750 Ω 750 Ω 49.9 Ω 150
+10 750 Ω 82.5 Ω 49.9 Ω 40
R
T
chosen for 50 Ω characteristic input impedance.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

AD8012ARZ-REEL

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Manufacturer:
Analog Devices Inc.
Description:
High Speed Operational Amplifiers Dual Low Power Current Feedback
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