GDDR5 SGRAM
EDW2032BBBG – 4 Meg x 32 I/O x 16 banks, 8 Meg x 16 I/O x 16 banks
Features
• V
DD
= V
DDQ
= 1.6V/1.5V ±3% and 1.35V ±3%
• Data rate: 5.0 Gb/s, 6.0 Gb/s, 7.0 Gb/s (MAX)
• 16 internal banks
• Four bank groups for
t
CCDL = 3
t
CK
• 8n-bit prefetch architecture: 256-bit per array read
or write access for x32; 128-bit for x16
• Burst length (BL): 8 only
• Programmable CAS latency: 6–22
• Programmable WRITE latency: 3–7
• Programmable CRC READ latency: 1–3
• Programmable CRC WRITE latency: 8–14
• Programmable EDC hold pattern for CDR
• Precharge: Auto option for each burst access
• Auto refresh and self refresh modes
• Refresh cycles: 16,384 cycles/32ms
• Interface: Pseudo open drain (POD-15) compatible
outputs: 40Ω pull-down, 60Ω pull-up
• On-die termination (ODT): 60Ω or 120Ω (NOM)
• ODT and output driver strength auto calibration
with external resistor ZQ pin: 120Ω
• Programmable termination and driver strength off-
sets
• Selectable external or internal V
REF
for data inputs;
programmable offsets for internal V
REF
• Separate external V
REF
for address/command in-
puts
• T
C
= 0°C to +95°C
• x32/x16 mode configuration set at power-up with
EDC pin
• Single-ended interface for data, address, and com-
mand
• Quarter data rate differential clock inputs CK_t,
CK_c for address and commands
• Two half data rate differential clock inputs, WCK_t
and WCK_c, each associated with two data bytes
(DQ, DBI_n, EDC)
• DDR data (WCK) and addressing (CK)
• SDR command (CK)
• Write data mask function via address bus (single/
double byte mask)
• Data bus inversion (DBI) and address bus inversion
(ABI)
• Input/output PLL on/off mode
• Duty cycle corrector (DCC) for data clock (WCK)
• Address training: Address input monitoring via DQ
pins
• WCK2CK clock training: Phase information via EDC
pins
• Data read and write training via read FIFO (FIFO
depth = 6)
• Read FIFO pattern preloaded by LDFF command
• Direct write data load to read FIFO by WRTR com-
mand
• Consecutive read of read FIFO by RDTR command
• Read/write data transmission integrity secured by
cyclic redundancy check (CRC-8)
• Read/write EDC on/off mode
• Low power modes
• RDQS mode on EDC pin
• On-die temperature sensor with readout
• Automatic temperature sensor controlled self
refresh rate
• Digital RAS lockout
• Vendor ID, FIFO depth and density info fields for
identification
• Mirror function with MF pin
• Boundary scan function with SEN pin
Options
1
Marking
• Organization
– Density 20
– 64 Meg x 32 (words x bits) 32
• FBGA package
– 170-ball (12mm x 14mm) BG
• Package environment code
– Lead- and halogen-free
(RoHS-compliant)
-F
• Package media
– Dry pack (tray) -D
– Reel -R
• Timing – Cycle time
– 5.0 Gb/s, 4.0 Gb/s -50
– 6.0 Gb/s, 5.0 Gb/s -6A
– 7.0 Gb/s, 5.5 Gb/s -7A
• Operating temperature
– Commercial (0°C ≤ T
C
≤ +95°C) None
• Revision B
Note:
1. Not all options listed can be combined to
define an offered product. Use the part
catalog search on http://www.micron.com
for available offerings.
2Gb: x16, x32 GDDR5 SGRAM
Features
PDF: 09005aef858b7e99
2gb_gddr5_sgram_brief.pdf - Rev. A 2/14 EN
1
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2014 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
