Table 2: 170-Ball FBGA Ball Descriptions
Symbol Type Description
A[12:0] Input Address inputs: Provide the row address for ACTIVE commands. A[5:0] (A6) provide
the column address and A8 defines the auto precharge bit for READ/WRITE com-
mands, to select one location out of the memory array in the respective bank. A8
sampled during a PRECHARGE command determines whether the PRECHARGE ap-
plies to one bank (A8 LOW, bank selected by BA[3:0]) or all banks (A8 HIGH). The ad-
dress inputs also provide the op-code during a MODE REGISTER SET command and
the data bits during LDFF commands. A[12:8] are sampled with the rising edge of
CK_t and A[7:0] are sampled with the rising edge of CK_c.
ABI_n Input Address bus inversion: Reduces the power requirements on address pins by limit-
ing the number of address lines driving LOW to 5. ABI_n is enabled by the corre-
sponding ABI mode register bit.
BA[3:0] Input Bank address inputs: Define the bank to which an ACTIVE, READ, WRITE, or PRE-
CHARGE command is being applied. BA[3:0] define which mode register is loaded
during the MODE REGISTER SET command. BA[3:0] are sampled with the rising edge
of CK_t.
CK_t, CK_c Input Clock: CK_t and CK_c are differential clock inputs. Command inputs are latched on
the rising edge of CK_t. Address inputs are latched on the rising edge of CK_t and
the rising edge of CK_c. All latencies are referenced to CK_t. CK_t and CK_c are ex-
ternally terminated.
WCK01_t, WCK01_c/
WCK23_t, WCK23_c
Input Data Clocks: WCK_t and WCK_c are differential clocks used for write data capture
and read data output. WCK01_t and WCK01_c are associated with DQ[15:0], DBI0_n,
DBI1_n, EDC0, and EDC1. WCK23_t and WCK23_c are associated with DQ[31:16],
DBI2_n, DBI3_n, EDC2, and EDC3. WCK clocks operate at nominally twice the CK
clock frequency.
CKE_n Input Clock enable: CKE_n enables (registered LOW) and disables (registered HIGH) inter-
nal circuitry and clocks on the SGRAM. The specific circuitry that is enabled/disabled
is dependent upon the device configuration and operating mode. Taking CKE_n
HIGH provides PRECHARGE POWER-DOWN and SELF REFRESH operations (all banks
idle), or active power-down (row active in any bank). CKE_n is synchronous for pow-
er-down entry and exit and for self refresh entry. CKE_n must be maintained LOW
throughout read and write accesses. Input buffers (excluding CKE_n) are disabled
during SELF REFRESH operation. The value of CKE_n latched at power-up with RE-
SET_n going HIGH determines the termination value of the address and command
inputs.
CS_n Input Chip select: CS_n enables (registered LOW) and disables (registered HIGH) the
command decoder. All commands are masked when CS_n is registered HIGH, but in-
ternal command execution continues. CS_n is considered part of the command code.
MF Input Mirror function: V
DDQ
CMOS input. Must be tied to V
DDQ
or V
SS
.
RAS_n, CAS_n, WE_n Input Command inputs: RAS_n, CAS_n, and WE_n (along with CS_n) define the com-
mand being entered.
RESET_n Input Reset: RESET_n is an active LOW CMOS input referenced to V
SS
. A full chip reset may
be performed at any time by pulling RESET_n LOW. With RESET_n LOW all ODTs are
disabled.
SEN Input Scan enable: V
DDQ
CMOS input. Must be tied to V
SS
when not in use.
2Gb: x16, x32 GDDR5 SGRAM
Ball Assignments and Descriptions
PDF: 09005aef858b7e99
2gb_gddr5_sgram_brief.pdf - Rev. A 2/14 EN
5
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2014 Micron Technology, Inc. All rights reserved.
