10
FN8202.1
July 28, 2006
Up/Down Interface Operation
The SCL, U/D, CS, DS0 and DS1 inputs control the
movement of the wiper along the resistor array. With CS
set
LOW the device is selected and enabled to respond to the
U/D
and SCL inputs. HIGH to LOW transitions on SCL will
increment or decrement (depending on the state of the U/D
input) a wiper counter register selected by DS0 and DS1.
The output of this counter is decoded to select one of 256
wiper positions along the resistor array.
The value of the counter is stored in nonvolatile data register
Level 0 of the corresponding WCR whenever CS
transitions
HIGH while the SCL and WP
inputs are HIGH (See Table 1).
During a “Store” operation bits WCRSel1 and WCRSel0 in
the status register must be both “0”, which is their power up
default value. Other combinations are reserved and must not
be used.
The system may select the X9455, move a wiper, and
deselect the device without having to store the latest wiper
position in nonvolatile memory. After the wiper movement is
performed as described above and once the new position is
reached, the system must keep SCL LOW while taking CS
HIGH. The new wiper position is maintained until changed
by the system or until a power-down/up cycle recalled the
previously stored data.
This procedure allows the system to always power-up to a
preset value stored in nonvolatile memory; then during
system operation minor adjustments could be made. The
adjustments might be based on user preference, system
parameter changes due to temperature drift, etc.
The state of U/D
may be changed while CS remains LOW.
This allows the host system to enable the device and then
move the wiper up and down until the proper trim is attained.
The 2-wire interface is disabled while CS
remains LOW.
*While in Standby, the 2-wire interface is enabled
TABLE 1. DCP SELECTION FOR UP/DOWN CONTROL
DS1 DS0
SELECTED WIPER
CONTROL REGISTER
0 0 Wiper A of DCP0
1 1 Wiper B of DCP0
1 0 Wiper A of DCP1
0 1 Wiper B of DCP1
TABLE 2. MODE SELECTION FOR UP/DOWN CONTROL
CS
SCL U/D MODE
L H Wiper Up
L L Wiper Down
H X Store Wiper Position to nonvolatile
memory if WP
pin is high. No store,
return to standby, if WP
pin is low.
H X X Standby*
L X No Store, Return to Standby
L H Wiper Up (not recommended)
L L Wiper Down (not recommended)
X9455
11
FN8202.1
July 28, 2006
2-Wire serial interface
Protocol Overview
The device supports a bidirectional bus oriented protocol.
The protocol defines any device that sends data onto the
bus as a transmitter, and the receiving device as the
receiver. The device controlling the transfer is called the
master and the device being controlled is called the slave.
The master always initiates data transfers, and provides the
clock for both transmit and receive operations. The X9455
operates as a slave in all applications.
All 2-wire interface operations must begin with a START,
followed by a Slave Address byte. The Slave Address
selects the X9455, and specifies if a Read or Write operation
is to be performed.
All Communication over the 2-wire interface is conducted by
sending the MSB of each byte of data first.
Serial Clock and Data
Data states on the SDA line can change only while SCL is
LOW. SDA state changes while SCL is HIGH are reserved
for indicating START and STOP conditions (See Figure 2).
On power up of the X9455, the SDA pin is in the input mode.
Serial Start Condition
All commands are preceded by the START condition, which
is a HIGH to LOW transition of SDA while SCL is HIGH. The
device continuously monitors the SDA and SCL lines for the
START condition and does not respond to any command
until this condition has been met (See Figure 2).
Serial Stop Condition
All communications must be terminated by a STOP
condition, which is a LOW to HIGH transition of SDA while
SCL is HIGH. The STOP condition is also used to place the
device into the Standby power mode after a read sequence.
A STOP condition can only be issued after the transmitting
device has released the bus (See Figure 2).
Serial Acknowledge
An ACK (Acknowledge), is a software convention used to
indicate a successful data transfer. The transmitting device,
either master or slave, releases the bus after transmitting
eight bits. During the ninth clock cycle, the receiver pulls the
SDA line LOW to acknowledge the reception of the eight bits
of data (See Figure 3).
The device responds with an ACK after recognition of a
START condition followed by a valid Slave Address byte. A
valid Slave Address byte must contain the Device Type
Identifier 0101, and the Device Address bits matching the
logic state of pins A2, A1, and A0 (See Figure 4).
If a write operation is selected, the device responds with an
ACK after the receipt of each subsequent eight-bit word.
In the read mode, the device transmits eight bits of data,
releases the SDA line, and then monitors the line for an
ACK. The device continues transmitting data if an ACK is
detected. The device terminates further data transmissions if
an ACK is not detected. The master must then issue a STOP
condition to place the device into a known state.
SDA
SCL
START DATA DATA STOP
STABLE CHANGE
DATA
STABLE
FIGURE 2. VALID DATA CHANGES, START, AND STOP CONDITIONS
SDA Output from
Transmitter
SDA Output from
Receiver
81 9
START ACK
SCL from Master
FIGURE 3. ACKNOWLEDGE RESPONSE FROM RECEIVER
X9455
12
FN8202.1
July 28, 2006
Slave Address Byte
Following a START condition, the master must output a
Slave Address Byte (Refer to figure 4.). This byte includes
three parts:
The four MSBs (SA7-SA4) are the Device Type Identifier,
which must always be set to 0101 in order to select the
X9455.
The next three bits (SA3-SA1) are the Device Address bits
(AS2-AS0). To access any part of the X9455’s memory,
the value of bits AS2, AS1, and AS0 must correspond to
the logic levels at pins A2, A1, and A0 respectively.
The LSB (SA0) is the R/W
bit. This bit defines the
operation to be performed on the device being addressed.
When the R/W
bit is “1”, then a Read operation is
selected. A “0” selects a Write operation.
Nonvolatile Write Acknowledge Polling
After a nonvolatile write command sequence is correctly
issued (including the final STOP condition), the X9455
initiates an internal high voltage write cycle. This cycle
typically requires 5 ms. During this time, any Read or Write
command is ignored by the X9455. Write Acknowledge
Polling is used to determine whether a high voltage write
cycle is completed.
During acknowledge polling, the master first issues a START
condition followed by a Slave Address Byte. The Slave
Address Byte contains the X9455’s Device Type Identifier
and Device Address. The LSB of the Slave Address (R/W
)
can be set to either 1 or 0 in this case. If the device is busy
within the high voltage cycle, then no ACK is returned. If the
high voltage cycle is completed, an ACK is returned and the
master can then proceed with a new Read or Write
operation. (Refer to figure 5.)
2-Wire Serial Interface Operation
X9455 Digital Potentiometer Register Organization
Refer to the Functional Diagram on page 1. There are 2
Digital Potentiometers, referred to as DCP0, and DCP1.
Each potentiometer has two volatile Wiper Control Registers
(WCRs). Each wiper has four non-volatile registers to store
wiper position or general data. See Table 2 for register
numbering.
SA6SA7
SA5
SA3 SA2
SA1
SA0
Device Type
Identifier
Read or
SA4
SLAVE ADDRESS
BIT(S) DESCRIPTION
SA7-SA4 Device Type Identifier
SA3-SA1 Device Address
SA0 Read or Write Operation Select
R/W0101
Address
Device
AS0AS1AS2
Write
FIGURE 4. SLAVE ADDRESS (SA) FORMAT
ACK returned?
Issue Slave Address
Byte (Read or Write)
Byte load completed by issuing
STOP. Enter ACK Polling
Issue STOP
Issue START
NO
YES
NO
Continue normal Read or Write
command sequence
PROCEED
YES
complete. Continue command
sequence.
High Voltage
Issue STOP
FIGURE 5. ACKNOWLEDGE POLLING SEQUENCE
X9455

X9455UV24IZ-2.7

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
IC POT DUAL 2WIPER 50K 24-TSSOP
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union