OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

X9455UV24IZ-2.7

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19
7
FN8202.1
July 28, 2006
Increment/Decrement Timing
NOTES:
1. Absolute linearity is utilized to determine actual wiper voltage versus expected voltage = [V(R
W(n)(actual)
)-V(R
W(n)(expected)
)]/MI
V(R
W(n)(expected)
) = n(V(R
H
)-V(R
L
))/255 + V(R
L
), with n from 0 to 255.
2. Relative linearity is a measure of the error in step size between taps = [V(R
W(n+1)
)-(V(R
W(n)
) + MI)]/MI, with n from 0 to 254
3. 1 Ml = Minimum Increment = [V(R
H
)-V(R
L
)]/255.
4. Typical values are for T
A
= 25C and nominal supply voltage.
5. This parameter is not 100% tested.
6. Ratiometric temperature coefficient = (V(R
W
)
T1(n)
-V(R
W
)
T2(n)
)/[V(R
W
)
T1(n)
(T1-T2)] x 10
6
, with T1 & T2 being 2 temperatures, and n from 0 to
255.
7. Measured with wiper at tap position 255, R
L
grounded, using test circuit.
8. t
WC
is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used. It is the time from a valid
STOP condition at the end of a write sequence of a 2-wire interface write operation, or from the rising edge of CS
of a valid “Store” operation of
the Up/Down interface, to the end of the self-timed internal nonvolatile write cycle.
9. The recommended power up sequence is to apply V
CC
/V
SS
first, then the potentiometer voltages. During power up, the data sheet parameters
for the DCP do not fully apply until t
D
after V
CC
reaches its final value. In order to prevent unwanted tap position changes, or an inadvertant
store, bring the CS
pin high before or concurrently with the V
CC
pin on power up.
CS
SCL
U/D
R
W
t
CI
t
IL
t
IH
t
CYC
t
ID
t
DI
t
IW
MI
(3)
t
IC
t
CPHS
t
F
t
R
10%
90% 90%
t
CPHNS
DS0, DS1
High-Voltage Write Cycle Timing
SYMBOL PARAMETER TYP MAX UNITS
t
WC
(Notes 5, 8)
Non-volatile write cycle time 5 10 ms
XDCP Timing
SYMBOL PARAMETER MIN MAX UNITS
t
WRL
(Note 5) SCL rising edge to wiper code changed, wiper response time after instruction
issued (all load instructions)
520µs
X9455
8
FN8202.1
July 28, 2006
Test Circuit
Equivalent Circuit
Pin Descriptions
Bus Interface Pins
Serial Data Input/Output (SDA)
The SDA is a bidirectional serial data input/output pin for the
2-wire interface. It receives device address, operation code,
wiper register address and data from a 2-wire external
master device at the rising edge of the serial clock SCL, and
it shifts out data after each falling edge of the serial clock
SCL.
SDA requires an external pull-up resistor, since it’s an open
drain output.
Serial Clock (SCL)
This input is the serial clock of the 2-wire and Up/Down
interface.
Device Address (A2-A0)
The Address inputs are used to set the least significant 3 bits
of the 8-bit 2-wire interface slave address. A match in the
slave address serial data stream must be made with the
Address input pins in order to initiate communication with the
X9455. A maximum of 8 devices may occupy the 2-wire
serial bus.
Chip Select (CS
)
When the CS
pin is low, increment or decrement operations
are possible using the SCL and U/D
pins. The 2-wire
interface is disabled at this time. When CS
is high, the 2-wire
interface is enabled.
Up or Down Control (U/D
)
The U/D
input pin is held HIGH during increment operations
and held LOW during decrement operations.
DCP Select (DS1-DS0)
The DS1-DS0 select one of the four DCPs for an Up/Down
interface operation.
Hardware Write Protect Input (WP
)
When the WP
pin is set low, “write” operations to non volatile
DCP Data Registers are disabled. This includes both 2-wire
interface non-volatile “Write”, and Up/Down interface “Store”
operations.
DCP Pins
R
H0
, R
L0
, R
H1
, R
L1
These pins are equivalent to the terminal connections on
mechanical potentiometers. Since there are two DCPs, there
is one set of R
H
and R
L
for each DCP.
R
W0A
, R
W0B
, R
W1A
, and R
W1B
The wiper pins are equivalent to the wiper terminals of
mechanical potentiometers. Since there are two wipers per
DCP, there are four R
W
pins.
Force
Current
Test Point
R
W
C
H
C
L
R
W
R
TOTAL
C
W
R
H
R
L
X9455
9
FN8202.1
July 28, 2006
Principles of Operation
The X9455 is an integrated circuit incorporating two resistor
arrays with dual wipers on each array, their associated
registers and counters, and the serial interface logic
providing direct communication between the host and the
digitally controlled potentiometers. This section provides
detail description of the following:
•Resistor Array
• Up/Down Interface
• 2-wire Interface
Resistor Array Description
The X9455 is comprised of two resistor arrays. Each array
contains 255 discrete resistive segments that are connected
in series. The physical ends of each array are equivalent to
the fixed terminals of a mechanical potentiometer (R
Hi
and
R
Li
inputs). (See Figure 1.)
Each array has two independent wipers. At both ends of
each array and between each resistor segment are two
switches, one connected to each of the wiper pins (R
WiA
and
R
WiB
).
Within each individual array only one switch of each wiper
may be turned on at a time.
These switches are controlled by two Wiper Counter
Register (WCR). The 8-bits of the WCR are decoded to
select and enable one of 256 switches. Note that each wiper
has a dedicated WCR. When all bits of a WCR are zeroes,
the switch closest to the corresponding R
L
pin is selected.
When all bits of a WCR are ones, the switch closest to the
corresponding R
H
pin is selected.
The WCRs are volatile and may be written directly. There
are four non-volatile Data Registers (DR) associated with
each WCR. Each DR can be loaded into WCR. All DRs and
WCRs can be read or written.
Power Up and Down Requirements
During power up CS must be high to avoid inadvertant
“store” operations. At power up, the contents of Data
Registers Level 0 (DR0A0, DR0B0, DR1A0, and DR1B0),
are loaded into the corresponding wiper counter register.
One of
WCRiA[7:0]
R
Hi
R
WiA
R
Li
= FF hex
255
254
255
256
Decoder
Volatile
8-bit
Wiper
Counter
Register
WCRiA
Four
Non-Volatile
Data
Registers
DRiA0, DRiA1,
DRiA2, and
DRiA3
“i” is either 0 or 1
WCRiB[7:0]
= 00 hex
1
0
R
WiB
254
0
1
WCRiB[7:0]
= FF hex
WCRiA[7:0]
= 00 hex
Volatile
8-bit
Wiper
Counter
Register
WCRiB
Four
Non-Volatile
Data
Registers
DRiB0, DRiB1,
DRiB2, and
DRiB3
2-wire and
Up/Down Interfaces
.
.
.
.
.
.
FIGURE 1. DETAILED BLOCK DIAGRAM OF ONE DCP
X9455
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19

X9455UV24IZ-2.7

Mfr. #:
Buy X9455UV24IZ-2.7
Manufacturer:
Renesas / Intersil
Description:
IC POT DUAL 2WIPER 50K 24-TSSOP
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet