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X9455UV24IZ-2.7

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19
13
FN8202.1
July 28, 2006
The registers are organized in pages of four, with one page
consisting of the four volatile WCRs, a second page
consisting of the Level 0 Data Registers, and so forth. These
pages can be written four bytes at time. In this manner all
four potentiometer WCRs can be updated in a single serial
write (see Page Write Operation), as well as all four registers
of a given page in the DR array.
The unique feature of the X9455 device is that writing or
reading to a Data Register of a given wiper automatically
updates the WCR of that wiper with the new value. In this
manner data can be moved from a particular wiper register
to that wiper’s WCR just by performing a 2-wire read
operation. Simultaneously, that data byte can be utilized by
the host.
Status Register Organization
The Status Register (SR) is used in read and write
operations to select the appropriate wiper register. Before
any wiper register can be accessed, the SR must be set to
the correct value. It is accessed by setting the Address Byte
to 07h. See Table 3. Do this by writing the slave address
followed by a byte address of 07h. The SR is volatile and
defaults to 00h on power up. It is an 8-bit register containing
three control bits in the 3 LSBs as follows:
Bits WCRSel1 and WCRSel0 determine which Data Register
of a wiper is selected for a given operation. NVEnable is
used to select the volatile WCR if “0”, and one of the non
volatile wiper registers if “1”. Table 3 shows this register
organization.
Wiper Addressing for 2-wire Interface
Once the Data Register Level has been selected by a 2-wire
instruction, then the wiper is determined by the Address Byte
of the following instruction. Note again that this enables a
complete page write of all four potentiometers at once a
particular Wiper Register has been chosen. The register
addresses accessible in the X9455 include:
TABLE 3. REGISTER NUMBERING
STATUS REG (NOTE 1)
(Addr: 07H) REGISTERED SELECTED (NOTE 2)
Reserved
bits 7-3
DRSel1
bit 2
DRSel0
bit 1
NVEnable
bit 0
DCP0 DCP2
(Addr: 00h) (Addr: 11h) (Addr: 02h) (Addr: 01h)
Reserved X X 0 WCR0A WCR0B WCR1A WCR1B
0 0 1 DR0A0 DR0B0 DR1A0 DR1B0
0 1 1 DR0A1 DR0B1 DR1A1 DR1B1
1 0 1 DR0A2 DR0B2 DR1A2 DR1B2
1 1 1 DR0A3 DR0B3 DR1A3 DR1B3
NOTES:To read or write the contents of a single Data Register or Wiper Register:
1. Load the status register (using a write command) to select the row. (See Figure 6.)
Writing a 1, 3, 5, or 7 to the Status Register specifies that the subsequent read or write command will access a Data Register. This Status
Register operation also initiates a transfer of the contents of the selected data register to its associated WCR for all DCPs. So, for example,
writing ‘03h’ to the status register causes the value in DR01 to move to WCR0, DR11 to move to WCR1, DR21 to move to WCR2, and DR31 to
move to WCR3.
Writing a 0 to bit ‘0’ of the Status Register specifies that the subsequent read or write command will access a Wiper Counter Register. Each
WCR can be written to individually, without affecting the contents of any other.
2. Access the desired DR or WCR using a new write or read command (see Figure 7 for write and Figure 9 for read.)
Specify the desired column (DCP number) by sending the DCP address as part of this read or write command.
76543 2 1 0
Reserved WCRSel1 WCRSel0 NVEnable
X9455
14
FN8202.1
July 28, 2006
All other address bits in the address byte must be set to “0”
during 2-wire write operations and their value should be
ignored when read.
Byte Write Operation
For any Byte Write operation, the X9455 requires the Slave
Address byte, an Address Byte, and a Data Byte (See Figure
7). After each of them, the X9455 responds with an ACK.
The master then terminates the transfer by generating a
STOP condition. At this time, if the write operation is to a
volatile register (WCR, or SR), the X9455 is ready for the
next read or write operation. If the write operation is to a
nonvolatile register (DR), and the WP
pin is high, the X9455
begins the internal write cycle to the nonvolatile memory.
During the internal nonvolatile write cycle, the X9455 does
not respond to any requests from the master. The SDA
output is at high impedance.
The SR bits and WP
pin determine the register being
accessed through the 2-wire interface. See Table 2 on page
9.
As noted before, any write operation to a Data Register
(DR), also transfers the contents of all the data registers in
that row to their corresponding WCR.
For example, to write 3Ahex to the Level 1 Data Register of
wiper 1A (DR1A1) the following sequence is required:
During the sequence of this example, WP
pin must be high,
and A0, A1, and A2 pins must be low. When completed, the
DR1A1 register and the WCR1A of Wiper 1A will be set to
3Ah, and the other data registers in Row 1 will transfer their
contents to the respective WCRs.
S
t
a
r
t
S
t
o
p
Slave
Address
Status Register
Address
Data
A
C
K
A
C
K
Signal at SDA
Signals from
the Slave
Signals from
the Master
0
A
C
K
If bit 0 of data byte = 1,
DR contents move to WCR
during this ACK period
0101
0 0 0 0 0 1 1 1 0 0 0 0 0 x x 1
DR select
FIGURE 6. STATUS REGISTER WRITE (USES STANDARD BYTE WRITE SEQUENCE TO SET UP ACCESS TO A DATA REGISTER)
TABLE 4. ADDRESSING FOR 2-WIRE INTERFACE ADDRESS
BYTE
ADDRESS (HEX) CONTENTS
0 Wiper 0A
1 Wiper 1B
2 Wiper 1A
3 Wiper 0B
4 Not Used
5 Not Used
6 Not Used
7 Status Register
START
Slave Address 0101 0000
ACK
Address Byte 0000 0111
ACK
Data Byte 0000 0011
ACK
(note: at this ACK, the WCRs are all updated with their
respective DR.)
STOP
START
Slave Address 0101 0000
ACK
Address Byte 0000 0010
ACK
Data Byte 0011 1010
ACK
STOP
(Hardware Address = 000,
and a Write command)
(Indicates Status Register
address)
(Data Register Level 1 and
NVEnable selected)
(Hardware address = 000,
(Access Wiper 1A)
(Write Data Byte 3Ah)
Write command)
X9455
15
FN8202.1
July 28, 2006
Page Write Operation
As stated previously, the memory is organized as a single
Status Register (SR), and four pages of four registers each.
Each page contains one Data Register for each wiper.
Normally a page write operation will be used to efficiently
update all four Data Registers and WCR in a single Write
command. Note the special sequence for writing to a page:
First wiper 0A, then 1B, then 1A, then 0B as shown in Figure
9.
In order to perform a Page Write operation to the memory
array, the NVEnable bit in the SR must first be set to “1”.
A Page Write operation is initiated in the same manner as
the Byte Write operation; but instead of terminating the write
cycle after the first data byte is transferred, the master can
transmit up to 4 bytes (See Figure 9). After the receipt of
each byte, the X9455 responds with an ACK, and the
internal WCR address is incremented by one. The page
address remains constant. When the address reaches the
end of the page, it “rolls over” and goes back to the first byte
of the same page.
For example, if the master writes three bytes to a page
starting at location DR1A2, the first two bytes are written to
locations DR1A2 and DR0B2, while the last byte is written to
location DR0A2. Afterwards, the WCR address would point
to location DR1B2. If the master supplies more than four
bytes of data, then new data overwrites the previous data,
one byte at a time.
The master terminates the loading of Data Bytes by issuing
a STOP condition, which initiates the nonvolatile write cycle.
As with the Byte Write operation, all inputs are disabled until
completion of the internal write cycle. If the WP
pin is low,
the nonvolatile write cycle doesn’t start and the bytes are
discarded.
Notice that the Data Bytes are also written to the WCR of the
corresponding WCRs, therefore in the above example,
WCR1A, WCR0B, and WCR0A are also written, and
WCR1B is updated with the contents of DR1B2.
S
t
a
r
t
S
t
o
p
Slave
Address
Address
Byte
Data
Byte
A
C
K
Signals from the
Master
Signals from the
Slave
A
C
K
0
0
011
A
C
K
Write
Signal at SDA
FIGURE 7. BYTE WRITE SEQUENCE
WCR WCR0A → WCR1B → WCR1A → WCR0B
DR Level 0 DR0A0 → DR1B0 → DR1A0 → DR0B0
DR Level 1 DR0A1 → DR1B1 → DR1A1 → DR0B1
DR Level 2 DR0A2 → DR1B2 → DR1A2 → DR0B2
DR Level 3 DR0A3 → DR1B3 → DR1A3 → DR0B3
FIGURE 8. PAGE WRITE SEQUENCE*
*Page writes may wrap around to the first address on a page from
the last address.
2 < n < 4
Signals from the
Master
Signals from the
Slave
Signal at SDA
S
t
a
r
t
Slave
Address
Address
Byte
A
C
K
A
C
K
0
0
011
Data Byte (1)
S
t
o
p
A
C
K
A
C
K
Data Byte (n)
Write
FIGURE 9. PAGE WRITE OPERATION
X9455
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19

X9455UV24IZ-2.7

Mfr. #:
Buy X9455UV24IZ-2.7
Manufacturer:
Renesas / Intersil
Description:
IC POT DUAL 2WIPER 50K 24-TSSOP
Lifecycle:
New from this manufacturer.
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