32-Mbit (2 M × 16/4 M × 8) Static RAM
CY62177ESL MoBL
®
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 001-64709 Rev. *E Revised November 17, 2015
32-Mbit (2 M × 16/4 M × 8) Static RAM
Features
■ Thin small outline package-I (TSOP-I) configurable as
2 M × 16 or as 4 M × 8 static RAM (SRAM)
■ High-speed up to 55 ns
■ Wide voltage range: 2.2 V to 3.6 V and 4.5 V to 5.5 V
■ Ultra low standby power
❐ Typical standby current: 3 µA
❐ Maximum standby current: 25 µA
■ Ultra low active power
❐ Typical active current: 4.5 mA at f = 1 MHz
■ Easy memory expansion with CE
1
, CE
2,
and OE Features
■ Automatic power-down when deselected
■ Complementary metal oxide semiconductor (CMOS) for
optimum speed and power
■ Available in Pb-free 48-ball TSOP-I package
Functional Description
The CY62177ESL is a high performance CMOS static RAM
organized as 2 M words by 16 bits and 4 M words by 8 bits. This
device features advanced circuit design to provide ultra low
active current. It is ideal for providing More Battery Life
(MoBL
®
) in portable applications such as cellular telephones.
The device also has an automatic power-down feature that
significantly reduces power consumption by 99 percent when
addresses are not toggling. The device can also be put into
standby mode when deselected (CE
1
HIGH or CE
2
LOW or both
BHE
and BLE are HIGH). The input and output pins (I/O
0
through
I/O
15
) are placed in a high impedance state when: deselected
(CE
1
HIGH or CE
2
LOW), outputs are disabled (OE HIGH), both
Byte High Enable and Byte Low Enable are disabled (BHE
, BLE
HIGH), or during a write operation (CE
1
LOW, CE
2
HIGH and WE
LOW).
To write to the device, take Chip Enables (CE
1
LOW and CE
2
HIGH) and Write Enable (WE) input LOW. If Byte Low Enable
(BLE
) is LOW, then data from I/O pins (I/O
0
through I/O
7
), is
written into the location specified on the address pins (A
0
through
A
20
). If Byte High Enable (BHE) is LOW, then data from I/O pins
(I/O
8
through I/O
15
) is written to the location specified on the
address pins (A
0
through A
20
). To read from the device, take
Chip Enables (CE
1
LOW and CE
2
HIGH) and Output Enable
(OE
) LOW while forcing the Write Enable (WE) HIGH. If Byte
Low Enable (BLE
) is LOW, then data from the memory location
specified by the address pins appear on I/O
0
to I/O
7
. If Byte High
Enable (BHE
) is LOW, then data from memory appears on I/O
8
to I/O
15
. See the Truth Table on page 11 for a complete
description of read and write modes.
For a complete list of related documentation, click here.
I/O
0
–I/O
7
ROW DECODER
A
8
A
7
A
6
A
5
A
2
SENSE AMPS
DATA IN
DRIVERS
OE
A
4
A
3
I/O
8
–I/O
15
WE
BLE
BHE
A
0
A
1
A
9
A
10
Power-
down
Circuit
BHE
BLE
CE
2
CE
1
CE
2
CE
1
BYTE
COLUMN DECODER
A
11
A
12
A
13
A
14
A
15
A
16
A
17
A
18
A
19
A
20
2 M × 16
RAM Array
Logic Block Diagram
