CY62177ESL MoBL
®
Document Number: 001-64709 Rev. *E Page 4 of 16
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Storage temperature ............................... –65 °C to + 150 °C
Ambient temperature with
power applied ......................................... –55 °C to + 125 °C
Supply voltage to ground
potential ....................................... –0.3 V to V
CC(max)
+ 0.3 V
DC voltage applied to outputs
in high Z state
[5, 6]
....................... –0.3 V to V
CC(max)
+ 0.3 V
DC input voltage
[5, 6]
................... –0.3 V to V
CC(max)
+ 0.3 V
Output current into outputs (LOW) ............................. 20 mA
Static discharge voltage
(per MIL-STD-883, method 3015) ......................... 2001 V
Latch-up current 200 mA
Operating Range
Device Range
Ambient
Temperature
V
CC
[7]
CY62177ESL Industrial –40 °C to +85 °C 2.2 V to 3.6 V
and
4.5 V to 5.5 V
Electrical Characteristics
Over the operating range
Parameter Description Test Conditions
55 ns
Unit
Min Typ
[8]
Max
V
OH
Output HIGH voltage 2.2 V V
CC
2.7 V I
OH
= –0.1 mA 2.0 V
2.7 V V
CC
3.6 V I
OH
= –1.0 mA 2.4 V
4.5 V V
CC
5.5 V I
OH
= –1.0 mA 2.4 V
V
OL
Output LOW voltage 2.2 V V
CC
2.7 V I
OL
= 0.1 mA 0.4 V
2.7 V V
CC
3.6 V I
OL
= 2.1 mA 0.4 V
4.5 V V
CC
5.5 V I
OL
= 2.1 mA 0.4 V
V
IH
Input HIGH voltage 2.2 V V
CC
2.7 V 1.8 V
CC
+ 0.3 V V
2.7 V V
CC
3.6 V 2.2 V
CC
+ 0.3 V V
4.5 V V
CC
5.5 V 2.2 V
CC
+ 0.3 V V
V
IL
Input LOW voltage 2.2 V V
CC
2.7 V –0.3 0.6 V
2.7 V V
CC
3.6 V –0.3 0.7
[9]
V
4.5 V V
CC
5.5 V –0.3 0.7
[9]
V
I
IX
Input leakage current GND V
I
V
CC
–1 +1 A
I
OZ
Output leakage current GND V
O
V
CC
, Output disabled –1 +1 A
I
CC
V
CC
operating supply current f = f
Max
= 1/t
RC
V
CC
= V
CC(max)
I
OUT
= 0 mA
CMOS levels
–3545mA
f = 1 MHz 4.5 5.5 mA
I
SB2
[10]
Automatic power-down
current — CMOS inputs
CE
1
V
CC
– 0.2 V or CE
2
0.2 V or
(BHE
and BLE) V
CC
– 0.2 V,
V
IN
V
CC
– 0.2 V or V
IN
0.2 V,
f = 0, V
CC
= 3.6 V
–325A
Notes
5. V
IL(min)
= –2.0 V for pulse durations less than 20 ns.
6. V
IH(max)
= V
CC
+ 0.75 V for pulse durations less than 20 ns.
7. Full Device AC operation assumes a 100 s ramp time from 0 to V
CC
(min) and 200 s wait time after V
CC
stabilization.
8. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
CC
= 3 V, and V
CC
= 5 V, T
A
= 25 °C
9. Under DC conditions the device meets a V
IL
of 0.8 V. However, in dynamic conditions Input LOW voltage applied to the device must not be higher than 0.7 V.
10. Chip enables (CE
1
and CE
2
), byte enables (BHE and BLE) and BYTE must be tied to CMOS levels to meet the I
SB2
/ I
CCDR
spec. Other inputs can be left floating.
CY62177ESL MoBL
®
Document Number: 001-64709 Rev. *E Page 5 of 16
Capacitance
Parameter
[11]
Description Test Conditions Max Unit
C
IN
Input capacitance T
A
= 25 °C, f = 1 MHz, V
CC
= V
CC(typ)
15 pF
C
OUT
Output capacitance 15 pF
Thermal Resistance
Parameter
[11]
Description Test Conditions TSOP I Unit
JA
Thermal resistance
(junction to ambient)
Still air, soldered on a 3 × 4.5 inch, four-layer printed circuit
board
55.91 C/W
JC
Thermal resistance
(junction to case)
9.39 C/W
AC Test Loads and Waveforms
Figure 2. AC Test Loads and Waveforms
V
CC
V
CC
Output
R2
30 pF
Including
JIG and
scope
GND
90%
10%
90%
10%
Rise Time = 1 V/ns
Fall Time = 1 V/ns
Output V
Equivalent to: THEVENIN EQUIVALENT
All Input Pulses
R
TH
R1
Table 1. AC Test Loads
Parameter 2.5 V 3.0 V 5.0 V Unit
R1 16667 1103 1800
R2 15385 1554 990
R
TH
8000 645 639
V
TH
1.20 1.75 1.77 V
Note
11. Tested initially and after any design or process changes that may effect these parameters.
CY62177ESL MoBL
®
Document Number: 001-64709 Rev. *E Page 6 of 16
Data Retention Characteristics
Over the operating range
Parameter Description Conditions Min Typ
[12]
Max Unit
V
DR
V
CC
for data retention 1.5 V
I
CCDR
[13]
Data retention current V
CC
= 1.5 V,
CE
1
V
CC
– 0.2 V or CE
2
0.2 V
or
(BHE and BLE) V
CC
– 0.2 V,
V
IN
V
CC
– 0.2 V or V
IN
0.2 V
––17A
t
CDR
[14]
Chip deselect to data retention
time
–0ns
t
R
[15]
Operation recovery time 55 ns
Data Retention Waveform
Figure 3. Data Retention Waveform
[16]
t
CDR
V
DR
1.5 V
Data Retention Mode
t
R
CE
1
or
V
CC
BHE.BLE
or
V
CC(min)
V
CC(min)
CE
2
Notes
12. Typical values are included only for reference and are not guaranteed or tested. Typical values are measured at V
CC
= 3 V, and V
CC
= 5 V, T
A
= 25 °C.
13. Chip enables (CE1
and CE2), byte enables (BHE and BLE) and BYTE must be tied to CMOS levels to meet the I
SB2
/ I
CCDR
spec. Other inputs can be left floating.
14. Tested initially and after any design or process changes that may affect these parameters.
15. Full device operation requires linear V
CC
ramp from V
DR
to V
CC(min)
100 s or stable at V
CC(min)
100 s.
16. BHE
.BLE is the AND of both BHE and BLE. Chip is deselected by either disabling the chip enable signals or by disabling both BHE and BLE.

CY62177ESL-55ZXI

Mfr. #:
Manufacturer:
Cypress Semiconductor
Description:
SRAM 32Mb 55ns 2M x 16 Low Power SRAM
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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