AD7683 Data Sheet
Rev. B | Page 12 of 16
APPLICATIONS INFORMATION
SW+MSB
16,384C
+IN
LSB
COMP
CONTROL
LOGIC
SWITCHES CONTROL
BUSY
OUTPUT CODE
CNV
REF
GND
–IN
4C 2C C C32,768C
SW–MSB
16,384C
LSB
4C 2C C C32,768C
04301-020
Figure 21. ADC Simplified Schematic
CIRCUIT INFORMATION
The AD7683 is a low power, single-supply, 16-bit ADC using a
successive approximation architecture.
The AD7683 is capable of converting 100,000 samples per
second (100 kSPS) and powers down between conversions.
When operating at 10 kSPS, for example, it consumes typically
150 µW with a 2.7 V supply, ideal for battery-powered
applications.
The AD7683 provides the user with an on-chip track-and-hold
and does not exhibit any pipeline delay or latency, making it
ideal for multiple, multiplexed channel applications.
The AD7683 is specified from 2.7 V to 5.5 V. It is housed in an
8-lead MSOP or a tiny, 8-lead QFN (LFCSP) package.
The AD7683 is an improved second source to the ADS8320 and
ADS8325. For even better performance, consider the AD7685.
CONVERTER OPERATION
The AD7683 is a successive approximation ADC based on a
charge redistribution DAC. Figure 21 shows the simplified
schematic of the ADC. The capacitive DAC consists of two
identical arrays of 16 binary-weighted capacitors that connect
to the two comparator inputs.
During the acquisition phase, terminals of the array tied to the
comparator’s input are connected to GND via SW+ and SW−.
All independent switches are connected to the analog inputs.
Thus, the capacitor arrays are used as sampling capacitors and
acquire the analog signal on the +IN and −IN inputs. When the
acquisition phase is complete and the
CS
input goes low, a con-
version phase is initiated. When the conversion phase begins,
SW+ and SW− are opened first. The two capacitor arrays are
then disconnected from the inputs and connected to the GND
input. Therefore, the differential voltage between the inputs,
+IN and −IN, captured at the end of the acquisition phase is
applied to the comparator inputs, causing the comparator to
become unbalanced. By switching each element of the capacitor
array between GND and REF, the comparator input varies by
binary-weighted voltage steps (V
REF
/2, V
REF
/4...V
REF
/65,536).
The control logic toggles these switches, starting with the MSB,
to bring the comparator back into a balanced condition. After
the completion of this process, the part returns to the acquisition
phase and the control logic generates the ADC output code.
TRANSFER FUNCTIONS
The ideal transfer function for the AD7683 is shown in Figure 22
and Table 10.
000...000
000...001
000...010
111...101
111...110
111...111
ADC CODE (STRAIGHT BINARY)
ANALOG INPUT
+FS – 1.5 LSB
+
FS – 1 LSB
–FS + 1 LSB
–FS
–FS + 0.5 LSB
04301-021
Figure 22. ADC Ideal Transfer Function
Table 10. Output Codes and Ideal Input Voltages
Description
Analog Input
V
REF
= 5 V
Digital Output Code
Hexadecimal
FSR 1 LSB 4.999924 V FFFF
1
Midscale + 1 LSB 2.500076 V 8001
Midscale 2.5 V 8000
Midscale 1 LSB 2.499924 V 7FFF
FSR + 1 LSB 76.3 µV 0001
FSR 0 V 0000
2
1
This is also the code for an overranged analog input (V
+IN
– V
IN
above
V
REF
– V
GND
).
2
This is also the code for an underranged analog input (V
+IN
– V
IN
below V
GND
).
Data Sheet AD7683
Rev. B | Page 13 of 16
04301-022
AD7683
REF
GND
VDD
–IN
+IN
DCLOCK
D
OUT
CS
3-WIRE INTERFACE
100nF
2.7V TO 5.25V
C
REF
2.2µF TO 10µF
(NOTE 2)
REF
0V TO V
REF
33
2.7nF
(NOTE 3)
(NOTE 4)
(NOTE 1)
NOTES
1. SEE VOLTAGE REFERENCE INPUT SECTION FOR REFERENCE SELECTION.
2. C
REF
IS USUALLY A 10µF CERAMIC CAPACITOR (X5R).
3. SEE DRIVER AMPLIFIER CHOICE SECTION.
4. OPTIONAL FILTER. SEE ANALOG INPUT SECTION.
Figure 23. Typical Application Diagram
TYPICAL CONNECTION DIAGRAM
Figure 23 shows an example of the recommended application
diagram for the AD7683.
ANALOG INPUT
Figure 24 shows an equivalent circuit of the input structure of
the AD7683. The two diodes, D1 and D2, provide ESD protec-
tion for the analog inputs, +IN and −IN. Care must be taken to
ensure that the analog input signal never exceeds the supply rails
by more than 0.3 V because this causes these diodes to become
forward-biased and start conducting current. However, these
diodes can handle a forward-biased current of 130 mA maximum.
For instance, these conditions can eventually occur when the
input buffer (U1) supplies are different from VDD. In such a
case, use an input buffer with a short-circuit current limitation
to protect the part.
04301-023
C
IN
R
IN
D1
D2
C
PIN
+IN
OR –IN
GND
VDD
Figure 24. Equivalent Analog Input Circuit
This analog input structure allows the sampling of the differen-
tial signal between +IN and −IN. By using this dierential input,
small signals common to both inputs are rejected. For instance,
by using −IN to sense a remote signal ground, ground potential
differences between the sensor and the local ADC ground are
eliminated. During the acquisition phase, the impedance of the
analog input, +IN, can be modeled as a parallel combination of
Capacitor C
PIN
and the network formed by the series connection
of R
IN
and C
IN
. C
PIN
is primarily the pin capacitance. R
IN
is typically
600 Ω and is a lumped component consisting of some serial
resistors and the on resistance of the switches. C
IN
is typically
30 pF and is mainly the ADC sampling capacitor. During the
conversion phase, when the switches are opened, the input
impedance is limited to C
PIN
. R
IN
and C
IN
make a 1-pole, low-
pass filter that reduces undesirable aliasing effects and limits
the noise.
When the source impedance of the driving circuit is low, the
AD7683 can be driven directly. Large source impedances signi-
ficantly affect the ac performance, especially THD. The dc
performances are less sensitive to the input impedance.
DRIVER AMPLIFIER CHOICE
Although the AD7683 is easy to drive, the driver amplifier
needs to meet the following requirements:
The noise generated by the driver amplifier needs to be
kept as low as possible to preserve the SNR and transition
noise performance of the AD7683. Note that the AD7683
has a noise figure much lower than most other 16-bit
ADCs and, therefore, can be driven by a noisier op amp
while preserving the same or better system performance.
The noise coming from the driver is filtered by the AD7683
analog input circuit, 1-pole, low-pass filter made by R
IN
and C
IN
or by the external filter, if one is used.
For ac applications, the driver needs to have a THD
performance suitable to that of the AD7683. Figure 16 shows
the THD vs. frequency that the driver should exceed.
For multichannel multiplexed applications, the driver
amplifier and the AD7683 analog input circuit must be
able to settle for a full-scale step of the capacitor array at a
16-bit level (0.0015%). In the amplifier data sheet, settling
at 0.1% to 0.01% is more commonly specified. This could
differ significantly from the settling time at a 16-bit level
and should be verified prior to driver selection.
Table 11. Recommended Driver Amplifiers
Amplifier Typical Application
ADA4841-1 Very low noise and low power
OP184 Low power, low noise, and low frequency
AD8605, AD8615 5 V single-supply, low power
AD8519 Low power and low frequency
AD8031 High frequency and low power
AD7683 Data Sheet
Rev. B | Page 14 of 16
VOLTAGE REFERENCE INPUT
The AD7683 voltage reference input, REF, has a dynamic input
impedance. Therefore, it should be driven by a low impedance
source with efficient decoupling between the REF and GND
pins, as explained in the Layout section.
When REF is driven by a very low impedance source (such as
an unbuffered reference voltage like the low temperature drift
ADR435 reference or a reference buffer using the AD8031 or
the AD8605), a 10 μF (X5R, 0805 size) ceramic chip capacitor is
appropriate for optimum performance.
If desired, smaller reference decoupling capacitors with values
as low as 2.2 μF can be used with a minimal impact on perfor-
mance, especially DNL.
POWER SUPPLY
The AD7683 powers down automatically at the end of each
conversion phase and, therefore, the power scales linearly with
the sampling rate, as shown in Figure 25. This makes the part
ideal for low sampling rates (even of a few Hz) and low battery-
powered applications.
1000
100
10
0.1
1
0.01
10 100 1k 10k 100k
04301-024
SAMPLING RATE (SPS)
OPERATING CURRENT (µA)
VDD = 2.7V
VDD = 5V
Figure 25. Operating Current vs. Sampling Rate
DIGITAL INTERFACE
The AD7683 is compatible with SPI®, QSPI™, digital hosts,
MICROWIRE™, and DSPs (for example, Blackfin® ADSP-BF531,
ADSP-BF532, ADSP-BF533, or the ADSP-2191M). The connection
diagram is shown in Figure 26 and the corresponding timing is
given in Figure 2.
A falling edge on
CS
initiates a conversion and the data transfer.
After the fifth DCLOCK falling edge, D
OUT
is enabled and forced
low. The data bits are then clocked, MSB first, by subsequent
DCLOCK falling edges. The data is valid on both DCLOCK
edges. Although the rising edge can be used to capture the data,
a digital host also using the DCLOCK falling edge allows a
faster reading rate, provided it has an acceptable hold time.
04301-025
CS
DCLOCK
D
OUT
DATA IN
CLK
CONVERT
DIGITAL HOST
AD7683
Figure 26. Connection Diagram
LAYOUT
Design the PCB that houses the AD7683 so that the analog and
digital sections are separated and confined to certain areas of
the board. The pin configuration of the AD7683, with all its
analog signals on the left side and all its digital signals on the
right side, eases this task.
Avoid running digital lines under the device because these
couple noise onto the die, unless a ground plane under the
AD7683 is used as a shield. Fast switching signals, such as
CS
or clocks, should never run near analog signal paths. Avoid
crossover of digital and analog signals.
Use at least one ground plane. It can be common or split between
the digital and analog sections. In such a case, it should be joined
underneath the AD7683.
The AD7683 voltage reference input (REF) has a dynamic input
impedance and should be decoupled with minimal parasitic
inductances. Accomplish this by placing the reference decoupling
ceramic capacitor close to, and ideally right up against, the REF
and GND pins and by connecting these pins with wide, low
impedance traces.
Finally, decouple the power supply, VDD, of the AD7683 with a
ceramic capacitor, typically 100 nF, placed close to the AD7683.
Connect it using short and large traces to provide low impedance
paths and reduce the effect of glitches on the power supply lines.
EVALUATING THE AD7683 PERFORMANCE
Other recommended layouts for the AD7683 are outlined in the
evaluation board for the AD7683 (EVAL-AD7683CBZ). The
evaluation board package includes a fully assembled and tested
evaluation board, documentation, and software for controlling
the board from a PC via the EVAL-CONTROL BRD3Z.

AD7683ARMZRL7

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 100 kSPS 16-BIT
Lifecycle:
New from this manufacturer.
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