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AD7683ARMZRL7

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
Data Sheet AD7683
Rev. B | Page 3 of 16
SPECIFICATIONS
VDD = 2.7 V to 5.5 V; V
REF
= VDD; T
A
= –40°C to +85°C, unless otherwise noted.
Table 2.
Parameter Conditions
AD7683 All Grades
Unit Min Typ Max
RESOLUTION 16 Bits
ANALOG INPUT
Voltage Range +IN − (–IN) 0 V
REF
V
Absolute Input Voltage +IN −0.1 VDD + 0.1 V
−IN −0.1 0.1 V
Analog Input CMRR f
IN
= 100 kHz 65 dB
Leakage Current at 25°C Acquisition phase 1 nA
Input Impedance See the Analog Input section
THROUGHPUT SPEED
Complete Cycle 10 µs
Throughput Rate 0 100 kSPS
DCLOCK Frequency 0 2.9 MHz
REFERENCE
Voltage Range 0.5 VDD + 0.3 V
Load Current 100 kSPS, V
+IN
− V
−IN
= V
REF
/2 = 2.5 V 50 µA
DIGITAL INPUTS
Logic Levels
V
IL
−0.3 0.3 × VDD V
V
IH
0.7 × VDD VDD + 0.3 V
I
IL
−1 +1 µA
I
IH
−1 +1 µA
Input Capacitance 5 pF
DIGITAL OUTPUTS
Data Format Serial, 16 bits straight binary
V
OH
I
SOURCE
= −500 µA VDD − 0.3 V
V
OL
I
SINK
= +500 µA 0.4 V
POWER SUPPLIES
VDD Specified performance 2.7 5.5 V
VDD Range
1
2.0 5.5 V
Operating Current 100 kSPS throughput
VDD
VDD = 5 V
800
VDD = 2.7 V 560 µA
Standby Current
2, 3
VDD = 5 V, 25°C 1 50 nA
Power Dissipation VDD = 5 V 4 6 mW
VDD = 2.7 V 1.5 mW
VDD = 2.7 V, 10 kSPS throughput
2
150
TEMPERATURE RANGE
Specified Performance T
MIN
to T
MAX
−40 +85 °C
1
See the Typical Performance Characteristics section for more information.
2
With all digital inputs forced to VDD or GND, as required.
3
During acquisition phase.
AD7683 Data Sheet
Rev. B | Page 4 of 16
VDD = 5 V; V
REF
= VDD; T
A
= –40°C to +85°C, unless otherwise noted.
Table 3.
Parameter Conditions
A Grade B Grade
Unit Min Typ Max Min Typ Max
ACCURACY
No Missing Codes 15 16 Bits
Integral Linearity Error −6 ±3 +6 −3 ±1 +3 LSB
Transition Noise 0.5 0.5 LSB
Gain Error
1
, T
MIN
to T
MAX
±2
±24
±2
±15
LSB
Gain Error Temperature Drift ±0.3 ±0.3 ppm/°C
Offset Error
1
, T
MIN
to T
MAX
±0.7 ±1.6 ±0.4 ±1.6 mV
Offset Temperature Drift ±0.3 ±0.3 ppm/°C
Power Supply Sensitivity
VDD = 5 V ± 5%
±0.05 ±0.05 LSB
AC ACCURACY
Signal-to-Noise f
IN
= 1 kHz 90 88 91 dB
2
Spurious-Free Dynamic Range f
IN
= 1 kHz −100 −108 dB
Total Harmonic Distortion f
IN
= 1 kHz −100 −106 dB
Signal-to-(Noise + Distortion) f
IN
= 1 kHz 90 88 91 dB
Effective Number of Bits f
IN
= 1 kHz 14.7 14.8 Bits
1
See the Terminology section. These specifications include full temperature range variation but do not include the error contribution from the external reference.
2
All specifications in dB are referred to a full-scale input, FS. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified.
VDD = 2.7 V; V
REF
= 2.5V; T
A
= –40°C to +85°C, unless otherwise noted.
Table 4.
A Grade B Grade
Parameter Conditions Min Typ Max Min Typ Max Unit
ACCURACY
No Missing Codes 15 16 Bits
Integral Linearity Error −6 ±3 +6 −3 ±1 +3 LSB
Transition Noise 0.85 0.85 LSB
Gain Error
1
, T
MIN
to T
MAX
±2 ±30 ±2 ±15 LSB
Gain Error Temperature Drift ±0.3 ±0.3 ppm/°C
Offset Error
1
, T
MIN
to T
MAX
±0.7 ±3.5 ±0.7 ±3.5 mV
Offset Temperature Drift ±0.3 ±0.3 ppm/°C
Power Supply Sensitivity
VDD = 2.7 V
±
5%
±0.05
±0.05
LSB
AC ACCURACY
Signal-to-Noise
f
IN
= 1 kHz
85
86
dB
2
Spurious-Free Dynamic Range f
IN
= 1 kHz −96 −100 dB
Total Harmonic Distortion f
IN
= 1 kHz −94 −98 dB
Signal-to-(Noise + Distortion) f
IN
= 1 kHz 85 86 dB
Effective Number of Bits f
IN
= 1 kHz 13.8 14 Bits
1
See the Terminology section. These specifications do include full temperature range variation but do not include the error contribution from the external reference.
2
All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified.
Data Sheet AD7683
Rev. B | Page 5 of 16
TIMING SPECIFICATIONS
VDD = 2.7 V to 5.5 V; T
A
= −40°C to +85°C, unless otherwise noted.
Table 5.
Parameter Symbol Min Typ Max Unit
Throughput Rate t
CYC
100 kHz
CS Falling to DCLOCK Low
t
CSD
0 μs
CS Falling to DCLOCK Rising
t
SUCS
20 ns
DCLOCK Falling to Data Remains Valid t
HDO
5 16 ns
CS Rising Edge to D
OUT
High Impedance
t
DIS
14 100 ns
DCLOCK Falling to Data Valid t
EN
16 50 ns
Acquisition Time t
ACQ
400 ns
D
OUT
Fall Time t
F
11 25 ns
D
OUT
Rise Time t
R
11 25 ns
Timing and Circuit Diagrams
04301-002
D
OUT
DCLOCK
COMPLETE CYCLE
POWER DOWN
CS
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
(MSB) (LSB)
HIGH-Z
0
HIGH-Z
t
ACQ
t
DIS
0
145
t
HDO
t
EN
t
CSD
t
SUCS
t
CYC
NOTES
1. A MINIMUM OF 22 CLOCK CYCLES ARE REQUIRED FOR 16-BIT CONVERSION. SHOWN ARE 24 CLOCK CYCLES.
D
OUT
GOES LOW ON THE DCLOCK FALLING EDGE FOLLOWING THE LSB READING.
Figure 2. Serial Interface Timing
04301-003
500µA I
OL
500µA I
OH
1.4V
T
O D
OUT
C
L
100pF
Figure 3. Load Circuit for Digital Interface Timing
0.8V
2V
2V
0.8V0.8V
2V
t
EN
t
EN
04301-004
Figure 4. Voltage Reference Levels for Timing
04301-006
D
OUT
90%
10%
t
R
t
F
Figure 5. D
OUT
Rise and Fall Timing
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

AD7683ARMZRL7

Mfr. #:
Buy AD7683ARMZRL7
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 100 kSPS 16-BIT
Lifecycle:
New from this manufacturer.
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