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AD7683ARMZRL7

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
AD7683 Data Sheet
Rev. B | Page 6 of 16
ABSOLUTE MAXIMUM RATINGS
Table 6.
Parameter Rating
Analog Inputs
+IN
1
, –IN
1
GND − 0.3 V to VDD + 0.3 V or
±130 mA
REF GND − 0.3 V to VDD + 0.3 V
Supply Voltages
VDD to GND −0.3 V to +6 V
Digital Inputs to GND −0.3 V to VDD + 0.3 V
Digital Outputs to GND
−0.3 V to VDD + 0.3 V
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
Lead Temperature Range JEDEC J-STD-20
Vapor Phase (60 sec) 215°C
Infrared (15 sec) 220°C
1
See the Analog Input section.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
Table 7. Thermal Resistance
Package Type θ
JA
θ
JC
Unit
8-Lead MSOP 200 44 °C/W
ESD CAUTION
Data Sheet AD7683
Rev. B | Page 7 of 16
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
04301-005
REF
1
+IN
2
–IN
3
GND
4
VDD
8
DCLOCK
7
D
OUT
6
CS
5
AD7683
TOP VIEW
(Not to Scale)
Figure 6. 8-Lead MSOP Pin Configuration
Table 8. 8-Lead MSOP Pin Function Descriptions
Pin No. Mnemonic Type
1
Function
1 REF AI
Reference Input Voltage. The REF range is from 0.5 V to VDD. It is referred to the GND pin. Decouple the
REF pin closely to the GND pin with a ceramic capacitor of a few μF.
2 +IN AI
Analog Input. It is referred to Pin –IN. The voltage range, that is, the difference between +IN and –IN, is 0 V
to V
REF
.
3 –IN AI Analog Input Ground Sense. Connect this pin to either the analog ground plane or a remote sense ground.
4 GND P Power Supply Ground.
5
CS
DI
Chip Select Input. On its falling edge, it initiates the conversions. The part returns to shutdown mode as
soon as the conversion is completed. It also enables D
OUT
. When high, D
OUT
is high impedance.
6 D
OUT
DO Serial Data Output. The conversion result is output on this pin. It is synchronized to DCLOCK.
7 DCLOCK DI Serial Data Clock Input.
8 VDD P Power Supply.
1
AI = analog input; DI = digital input; DO = digital output; and P = power.
04301-107
3–IN
4GND
1REF
2+IN
6D
OUT
5CS
NOTES
1. EXPOSED PAD. CONNECT THE EXPOSED PAD TO GND. THIS CONNECTION
IS NOT REQUIRED TO MEET SPECIFIED ELECTRICAL PERFORMANCE.
8VDD
7 DCLOCK
AD7683
TOP VIEW
(Not to Scale)
Figure 7. 8-Lead QFN (LFCSP) Pin Configuration
Table 9. 8-Lead QFN (LFCSP) Pin Function Descriptions
Pin No. Mnemonic Type
1
Function
1 REF AI
Reference Input Voltage. The REF range is from 0.5 V to VDD. It is referred to the GND pin. Decouple the
REF pin closely to the GND pin with a ceramic capacitor of a few μF.
2 +IN AI
Analog Input. It is referred to Pin –IN. The voltage range, that is, the difference between +IN and –IN, is 0 V
to V
REF
.
3 –IN AI Analog Input Ground Sense. Connect this pin to either the analog ground plane or a remote sense ground.
4 GND P Power Supply Ground.
5
CS
DI
Chip Select Input. On its falling edge, it initiates the conversions. The part returns to shutdown mode as
soon as the conversion is completed. It also enables D
OUT
. When high, D
OUT
is high impedance.
6 D
OUT
DO Serial Data Output. The conversion result is output on this pin. It is synchronized to DCLOCK.
7 DCLOCK DI Serial Data Clock Input.
8 VDD P Power Supply.
EPAD
Exposed Pad. Connect the exposed pad to GND. This connection is not required to meet specified
electrical performance.
1
AI = analog input; DI = digital input; DO = digital output; and P = power.
AD7683 Data Sheet
Rev. B | Page 8 of 16
TERMINOLOGY
Integral Nonlinearity Error (INL)
Linearity error refers to the deviation of each individual code
from a line drawn from negative full scale through positive
full scale. The point used as negative full scale occurs ½ LSB
before the first code transition. Positive full scale is defined as
a level 1½ LSB beyond the last code transition. The deviation
is measured from the middle of each code to the true straight
line (see Figure 22).
Differential Nonlinearity Error (DNL)
In an ideal ADC, code transitions are 1 LSB apart. DNL is the
maximum deviation from this ideal value. It is often specified in
terms of resolution for which no missing codes are guaranteed.
Offset Error
The first transition should occur at a level ½ LSB above analog
ground (38.1 µV for the 0 V to 5 V range). The offset error is
the deviation of the actual transition from that point.
Gain Error
The last transition (from 111...10 to 111...11) should occur for
an analog voltage 1½ LSB below the nominal full scale
(4.999886 V for the 0 V to 5 V range). The gain error is the
deviation of the actual level of the last transition from the ideal
level after the offset has been adjusted out.
Spurious-Free Dynamic Range (SFDR)
The difference, in decibels (dB), between the rms amplitude of
the input signal and the peak spurious signal.
Signal-to-(Noise + Distortion) Ratio (SINAD)
SINAD is the ratio of the rms value of the actual input signal to
the rms sum of all other spectral components below the Nyquist
frequency, including harmonics but excluding dc. The value for
SINAD is expressed in dB.
Effective Number of Bits (ENOB)
ENOB is a measurement of the resolution with a sine wave
input. It is related to SINAD (as represented by S/(N+D)) by
the following formula and is expressed in bits:
[
]
( )
02.6/76.1/ −+=
dB
DNSENOB
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal and is
expressed in dB.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the actual input signal to
the rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in dB.
Aperture Delay
Aperture delay is a measure of the acquisition performance and
is the time between the falling edge of the
CS
input and when
the input signal is held for a conversion.
Transient Response
Transient response is the time required for the ADC to
accurately acquire its input after a full-scale step function is
applied.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

AD7683ARMZRL7

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Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 100 kSPS 16-BIT
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