PDF: 09005aef81c737fb/Source: 09005aef81c7379d Micron Technology, Inc., reserves the right to change products or specifications without notice.
DVF9C64x72.fm - Rev. B 10/07 EN
6 ©2005 Micron Technology, Inc. All rights reserved.
512MB (x72, ECC, SR) 184-Pin DDR VLP RDIMM
General Description
General Description
The MT9VDVF6472 is a high-speed, CMOS, dynamic random access 512MB memory
module and is organized in a x72 configuration. This module uses a DDR SDRAM device
with four internal banks.
DDR SDRAM modules use a double data rate architecture to achieve high-speed opera-
tion. The double data rate architecture is essentially a 2n-prefetch architecture with an
interface designed to transfer two data words per clock cycle at the I/O pins. A single
read or write access for DDR SDRAM modules effectively consists of a single
2n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and two corre-
sponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins.
A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in
data capture at the receiver. DQS is a strobe transmitted by the DDR SDRAM during
READs and by the memory controller during WRITEs. DQS is edge-aligned with data for
READs and center-aligned with data for WRITEs.
DDR SDRAM modules operate from differential clock inputs (CK and CK#); the crossing
of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK.
Commands are registered at every positive edge of CK. Input data is registered on both
edges of DQS, and output data is referenced to both edges of DQS, as well as to both
edges of CK.
Register and PLL Operation
These DDR SDRAM modules operate in registered mode, where the command/address
input signals are latched in the registers on the rising clock edge and sent to the DDR
SDRAM devices on the following rising clock edge (data access is delayed by one clock
cycle). A phase-lock loop (PLL) on the module receives and redrives the differential clock
signals (CK, CK#) to the DDR SDRAM devices. The register(s) and PLL reduce address,
command, control, and clock signal loading by isolating DRAM from the system
controller. PLL clock timing is defined by JEDEC specifications and ensured by use of the
JEDEC clock reference board. Registered mode will add one clock cycle to CL.
Serial Presence-Detect Operation
DDR SDRAM modules incorporate serial presence-detect (SPD). The SPD function is
implemented using a 2,048-bit EEPROM. This nonvolatile storage device contains
256 bytes. The first 128 bytes are programmed by Micron to identify the module type and
various SDRAM organizations and timing parameters. The remaining 128 bytes of
storage are available for use by the customer. System READ/WRITE operations between
the master (system logic) and the slave EEPROM device (DIMM) occur via a standard I
2
C
bus using the DIMM’s SCL (clock) and SDA (data) signals, together with SA (2:0), which
provide eight unique DIMM/EEPROM addresses. Write protect (WP) is tied to V
SS on the
module, permanently disabling hardware write protect.
